Login

 T2M 
Part Number : DDR4/LPDDR4 Combo PHY in TSMC 12 FFC
Short Desc. : DDR4/LPDDR4 Combo PHY with Matching DDR4 Controller
Overview :

The DDR PHY IP supports DDR4/LPDDR4/DDR3L, provides low latency, and enables up to 3200Mbps throughput.The PHY IP is silicon proven and designed for ease of integration and faster time-to market


Features : - Supported DRAM type: DDR3L/DDR4/LPDDR4
- Maximum controller clock frequency of 800MHz resulting in maximum DRAM data rate of 3200Mbps Interface:
- SSTL135/POD12/LVSTL Data path width scales in 8-bit increment Four module for flexible configuration:
- Programmable output impedance(DS) Programmable on-die termination(ODT)
- Core power:0.8V
- ESD : 2KV/HBM, 200V/MM, 500V/CDM
- Support ZQ calibration
- Support 4 ranks by each CA module
- Support write-leveling, CBT Support PHY internal VREFDQ auto decision
- Per-bit deskew in read and write datapath
- TSMC 12nm FFC IP9M 2xa1xd3xe2z AL=28k (ULVT/SVT) process
- Flip-Chip
Categories :
Tags : DDR3L/DDR4/LPDDR4
Portability :
Type :
 Hard IP 
Foundry :
TSMC
Nodes :
12nm

Deliverables : - User Manual
- Behavior model, and RTL codes
- Protected Post layout netlist and Standard Delay Format (SDF)
- Synopsys library (LIB)
- Frame view (LEF)
- Metal GDS (GDSII)
- Test patterns and Test Documentation
- Verilog HDL



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise