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Part Number : |
RS Code for Error Correction FEC |
Short Desc. : |
Reed Solomon Code for Error Correction |
Overview : |
Zero latency, low gate count, low power, asynchronous Reed Solomon Code based Error Correcting FEC:
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Features : |
- "
- The main features are
- 1. Asynchronous operation
- 2. No clocks required.
- 3. No storage like memories SRAMS/ROMS/FilipFlops used
- 4. No iterative Feedback in the pipeline
- 5. All operation is performed in 0 clock cycles.
- 6. RTL code is generated with parameters of
- a) “m” the degree of primitive polynomial
- b) “t_max” maximum value of error symbols that can be corrected.
- c) number of symbols by which the code is shortened.
- d) The number of error symbols (“t”) is programmable upto
- “t_max” .
- 7. Separate encoders are for every “t” .
- 8. Decoder shared for various values of “t” upto “t_max”
- 9. Lint clean code, verified for various values of “m”, “t_max”, “t” and shortened code.
- 10. Size of code differs for various values of “m”, “t_max” and number of symbols by which the code is shortened.
- ."
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Categories : |
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Maturity : |
Verified, lint clean |
Portability : |
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Type : |
Soft |
Deliverables : |
- "RTL :
- Lint clean verified
- On request:
- Netlist generated
- Sample Testbench"
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