Mixel, Inc. 
Part Number : MXL-CDPHY-4p5G-UNIV-T-22ULP
Short Desc. : MIPI C-PHY/D-PHY Combo IP Universal, 4.5Gsps/4.5Gbps
Overview :

The MXL-CD-PHY-UNIV-T-22ULP is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for D-PHY v2.5 and C-PHY v2.0 The PHY can be configured as a MIPI Master or MIPI Slave supporting camera interface CSI-2 and display interface DSI/DSI-2. The PHY supports mobile, IoT, virtual reality, and automotive applications.

Mixel’s MIPI C-PHY v2.0 supports a speed of 4.5 Gsps per trio, an equivalent data rate of 10.26 Gbps/trio. In D-PHY mode, the IP supports speeds up to 4.5 Gbps per lane and complies with the MIPI D-PHY v2.5 specification. With up to three trios in C-PHY and up to four lanes in D-PHY, the combo IP reaches an aggregate bandwidth of 30.78 Gbps and 18Gbps in their respective modes.

The Mixel MIPI C-PHY/D-PHY Combo IP includes many new features to both the D-PHY and C-PHY that was not available in previous versions of the specifications, namely Spread Spectrum Clocking (SSC), transmit equalization (de-emphasis), and receiver ISI calibration. It also supports new power saving functionality such as HS-TX reduced swing modes and the HS-RX unterminated mode. The new Alternate LP Mode, suitable for IoT applications with long channels, is also supported, enabling Fast Bus Turnaround that boosts transmission bandwidth in the reverse direction of the MIPI link. The ALP Mode is central to the CSI-2 Unified Serial Link feature that reduces number of interface wires and helps to natively support longer reach. The combo PHY IP not only shares the serial interface pins, but Mixel’s implementation also reuses all the MIPI D-PHY functional blocks for the MIPI C-PHY, minimizing area and leakage power.

Features : - Dual mode PHY Supports MIPI Alliance Specification D-PHY v2.5 & C-PHY v2.0
- Consists of 1 Clock lane and 4 Data lanes in D-PHY mode
- Consists of 3 Data lanes in C-PHY mode
- Embedded, high performance, and highly programmable PLL
- PLL supports SSC mode, Fractional mode, and Integer mode
- Supports both low-power mode and high speed mode with integrated SERDES
- 80 Mbps to 1.5 Gbps data rate per lane without Deskew calibration in D-PHY mode
- 4.5 Gbps data rate per lane with Deskew calibration in high speed D-PHY mode
- 80 Msps to 4.5 Gsps symbol rate per lane in high speed C-PHY mode
- Supports High Speed TX De-emphasis Equalization
- Supports High Speed RX CTLE
- Supports High Speed Reverse Communication
- 10 Mbps data rate in low-power mode
- Low power dissipation
- Testability support including internal loopback
- Comprehensive embedded DFT features for allowing cost-effective high-volume manufacturing tests
- Supports full-speed loopback testability for high-volume manufacturing tests
- Calibrator for resistance termination
Categories :
Tags : mipi, dphy, d-phy, cphy, c-phy, csi, csi-2, csi2, dsi, dsi-2, dsi2, serdes, cdphy, c/d-phy
Maturity : Silicon Proven
Portability :
Type : Hard
Deliverables : - Specifications
- LVS netlist
- LEF file
- Verilog Model
- Timing Model
- Integration Guidelines
- Documentation
- One year support

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