Part Number : dwc_troot_f022_hsm
Short Desc. : tRoot F022 Hardware Secure Module (w/ ARC EM22FS)
Overview :

The ASIL B compliant DesignWare® tRoot™ Hardware Secure Module (HSM) for Automotive augments its comprehensive root of trust security solution with a suite of automotive documentation and hardware safety mechanisms to protect against malicious security attacks and random and systematic safety faults.

The tRoot HSM for Automotive includes a broad range of safety mechanisms such as dual-core lockstep, memory ECC, register EDC, parity, watchdog, self-checking comparators, bus and MPU protection, and dual rail logic. It incorporates an ASIL D compliant low-power ARC processor.

The tRoot HSM for Automotive is developed with an ASIL D systematic development flow and designed and assessed for ASIL B random hardware faults. The solution is provided with a complete suite of ISO 26262 documentation, including safety manual, DFMEA/FMEDA/DFA analysis reports, quality manual, and development interface report, making it a fully ASIL compliant solution.

Features : - Safety mechanisms for ASIL B compliance for random faults and ASIL D compliance for systematics
- Scalable cryptography AES/SHA/ECC/RSA acceleration from CPU custom instructions, to cryptographic cores – Symmetric (128/192/256-bit keys, encrypt/decrypt) – AES ECB/CBC/CTR/OFB/CFB/GCM/XTS with side channel (DPA) protection – ChaCha20 3 – Hash/MAC – SHA-1, SHA-224/256/384/512, SHA2-224/256/384/512, SHA-3 – Poly1305 – AES-GMAC, HMAC-SHA-256, AES-CMAC – Asymmetric with side channel (DPA/TA) protection – ECC (NIST/Brainpool up to 512/521-bit, C25519, Ed25519) – RSA (up to 4096-bit) – APEX AES/SHA/ECC/RSA cryptography acceleration (via CryptoPack)
- Efficient low-power ARC processor with SecureShieldTM technology that includes MPU
- Secure External Memory Controller, including Secure Instruction Memory Controller with side channel (DPA protection) and 256- bit security to provide confidentiality and integrity protection for untrusted external memory (e.g. RAM, flash), as well as runtime tamper detection
- NIST SP800-90c compliant TRNG
- Multiple secure key servers for secure key distribution within the SoC
- Compliant with EVITA Full/Medium/Light hardware requirements – Boot integrity protection, crypto algorithms with hardware acceleration, internal/programmable CPU, TRNG, tamper protection, etc.
- Host processor communication via shared memory, interrupts, HPI mailbox or UART
- Peripherals: GPIO, UART, APB
- Private AHB5 and APB4 security extension ports for customer IP/NVM
- Clock and reset management
- Power management support – Independent clock switching control for all I/O functions, crypto engines, and internal CPU
Categories :
Maturity : Available on request
Portability :
Type : Soft
Deliverables : - IPLib installation files
- Release notes
- Hardware (RTL), software source code, applications examples, tools
- Documentation – Data books/user guides/integration guides
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