Part Number : dwc_200g_400g_800g_ethernetmac_pcs
Short Desc. : DesignWare 200G/400G and 800G Ethernet MAC and PCS IP
Overview :

The DesignWare 200/400G and 800G Ethernet MAC and PCS IP solutions enable a host to transmit and receive data over Ethernet. The PCS IP is optimized for low latency and supports multi-rates for up to 8-lane and 1024- bit architecture, offering different interfaces and implementation tradeoffs. The DesignWare 200G/400G and 800G Ethernet MAC and PCS support IEEE 802.3 and consortium specifications including Reed Solomon Forward Error Correction (FEC) and timestamping with low jitter for maximum precision. The IP simplifies the chip level clock distribution and eliminates any clock muxing elements or PLLs that are typically used in multi-rate designs to create multiple frequency locked clocks with precise frequency.

The silicon proven DesignWare 200G/400G and 800G Ethernet MAC and PCS along with the DesignWare 56G and 112G Ethernet PHYs, and Verification IP provide a complete Ethernet solution that designers can easily integrate in large SoCs for high-performance computing, AI, and networking applications.

Features : - Configurable, multi-rate solution supporting Ethernet data rates from 1G to 800G
- Compliant with IEEE standards including: IEEE 802.3 1G to 400G speeds, IEEE 1588, IEEE 802.3az, Energy Efficient Ethernet (EEE), IEEE 802.1Qbb Priority-based Flow Control (PFC), Backplane Ethernet with Auto-Negotiation, Link Training and Forward Error Correction (FEC) options, Ethernet in First Mile (EFM) and Custom Preamble, Reed Solomon Forward Error Correction, Fire Code Forward Error Correction
- Configurable interfaces to the PHY layer supporting SMII, RMII, RGMII, SGMII, QSGMII, USGMII, ESXGMII, USXGMII-M interface
- Simplifies the chip level clock distribution and eliminates any clock muxing elements or PLLs
- Optimized for low latency
- Easy to use and integrate in large SoCs, able to freely place with any form factor
Categories :
Maturity : Available on request
Portability :
Type : Soft
Deliverables : - Synopsys coreConsultant tool
- Verilog RTL source code
- ASIC and FPGA synthesis, ATPG, DFT, power scripts
- Spyglass lint checker rules used for linting and example report
- UVM Testbench with native SystemVerilog Verification IP for Ethernet and a pin-compatible behavioral PHY model
- Comprehensive data book and integration guides

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