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 CAST, Inc. 
Part Number : BA51
Short Desc. : Low-Power Deeply Embedded RISC-V Processor
Overview :

The BA51 is a highly configurable, low-power deeply embedded RISC-V processor IP core. It implements a single-issue, in-order, 2-stage execution pipeline, supporting the RISC-V 32-bit base integer instruction set (RV32I), or the 32-bit base embedded instructions set (RV32E).
Configuration Options for Broad Application Support

The processor core can be configured to meet different application requirements. It can optionally support user and supervisor privilege modes, as well as the ISA extensions for Compressed Instructions (C), Integer Multiplication and Division instructions (M), Atomic Instructions (A), User-Level Interrupts (N), Control and Status Register (Zicsr), and Instruction-Fetch Fence (Zifencei). Support for the single-precision floating-point (F) ISA extension can also be added upon request.

Furthermore, the BA51 supports software and timer interrupts and up to 64 external interrupt lines. It features a remarkably low interrupt response time, which makes the core ideal for real-time control applications. The time elapsed from when an external interrupt is asserted until the first instruction in the resolved interrupt handler can be issued is just four clock cycles.

The user can minimize the core’s silicon footprint by choosing not to implement internal modules such as the machine mode internal timers and counters; the vectored interrupt controller (VIC); or the debug, power management (PMU), or memory protection (MPU) units. Finer-grained controls give customers the means to further tune the processor’s features and size to their specific design needs, including the number and size of memory regions for the MPU, the mapping of memory addresses to interfaces, and the width of the instruction and data buses.


Features : - Low-Power Embedded Processor
- Small silicon footprint for lower leakage and dynamic CPU power
- From 2.8 sq. ┬Ám in 16nm, or approximately 16k gates
- Advanced power management
- Dynamic clock gating and power shut off of unused units
- Software- and hardware-controlled clock frequency
- Single-issue, in-order, 2-stage pipeline
- Harvard architecture with separate instruction and data AXI- Lite and Quick-access Memory (QMEM) buses
- Performance
- 3.0 Coremarks/MHz
- Over 500 MHz in 16 nm
- RISC-V Features
- 32-bit Base RISC-V ISA (I/E) with optional M, A, Zicsr, Zifencei, C, and N Extensions
- F ISA extension upon request
- Supervisor, User, and Machine Modes
- Memory protection unit with configurable number of regions
- Core Local Interrupt Controller (CLINT) for time and software interrupts and Programmable or Vectored Interrupt Controller (PIC or VIC) for up to 64 direct external interrupts
Categories :
Tags : RISC-V, Low Power, Deeply Embedded
Maturity : Silicon proven
Portability :
Type : Soft
Deliverables : - Deliverables
- Available in Verilog source-code or as targeted FPGA netlist
- Comprehensive Documentation
- Testbench and sample simulation scripts



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