The DP8051 is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU. The DP8051 soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of DP8051: Harvard where internal data and program buses are separated, and von Neumann with common program and external data bus. The DP8051 has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51 with the same settings. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten times slower than the original implementation without performance depletion.