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 Digital Core Design 
Part Number : DP8051XP
Overview :

The DP8051XP is an ultra high performance, speed optimized soft core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU.
The DP8051XP soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of DP8051XP: Harvard where internal data and program buses are separated, and von Neumann with common program and external data bus. The DP8051XP has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51 with the same settings. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten times more slower than the original implementation, without performance depletion.


Features : 100% software compatible with industry standard 8051 Pipelined RISC architecture enables to execute 15.55 times faster than the original 80C51 at the same frequency Up to 14.632 VAX MIPS at 100 MHz 24 times faster multiplication 12 times faster division 2 Data Pointers (DPTR) for faster memory blocks copying:
  • Advanced INC & DEC modes
  • Auto-switch of current DPTR
Up to 256 bytes of internal (on-chip) Data Memory Up to 64 kB of internal (on-chip) or external (off-chip) Program Memory Up to 16 MB of external (off-chip) Data Memory:
  • Synchronous eXternal Data Memory (SXDM) Interface
User programmable Program Memory Wait States User programmable External Data Memory Wait States De-multiplexed Address/Data bus to allow easy memory connection Interface for additional Special Function Registers DoCD debug unit:
  • Processor execution control
  • Read-write all processor contents
  • Hardware execution breakpoints
  • JTAG communication interface
Power Management Unit:
  • Power management mode
  • Switchback feature
  • Stop mode
Interrupt Controller:
  • 2 priority levels
  • up to 7 external interrupt sources
  • up to 8 interrupt sources from peripherals
Four 8-bit I/O Ports:
  • Bit addressable data direction for each line
  • Read/write of single line and 8-bit group
Three 16-bit timer/counters:
  • Timers clocked by internal source
  • Auto reload 8-/16-bit timers
  • Externally gated event counters
Two full-duplex serial port:
  • Synchronous mode, fixed baud rate
  • 8-bit asynchronous mode, fixed baud rate
  • 9-bit asynchronous mode, fixed baud rate
  • 9-bit asynchronous mode, variable baud rate
I2C bus controller - Master up to 3.4Mbps I2C bus controller - Slave up to 3.4Mbps SPI – Master and Slave Serial Peripheral Interface Programmable Watchdog Timer 16-bit Compare/Capture Unit Floating-Point math coprocessor - IEEE-754 standard single precision real, word and short integers DMAC -10/100Mb Media Access controller DUSB2 - High Speed USB 2.0 device and more peripherals
Fully synthesizable Static synchronous design Positive edge clocking and no internal tri-states Scan test ready
Categories :
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria 10
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
ARRIA V GZ
ARRIA V ST
ARRIA V SX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
EP5C
FLEX 10K
HardCopy
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
HardCopy Stratix
MAX II
MAX V
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
STRATIX III E
Stratix IV
STRATIX IV E
STRATIX IV GT
STRATIX IV GX
Stratix V
STRATIX V E
STRATIX V GS
STRATIX V GT
STRATIX V GX
Lattice :
ispClock
ispMACH 4000
LatticeEC/ECP
LatticeECP2
LatticeECP2M
LatticeECP3
LatticeSC
LatticeSCM
LatticeXP
LatticeXP2
MachXO
MachXO2
Platform Manager
Power Manager II
Xilinx :
Artix-7
Kintex-7
Kintex-7 -2L
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type : Soft
Deliverables : - Source code: VHDL Source Code or/and VERILOG Source Code or/and FPGA Netlist
- VHDL & VERILOG test bench environment: Active HDL automatic simulation macros, ModelSim automatic simulation macros, NCSim automatic simulation macros, Tests with reference responses
- Technical documentation: Installation notes, HDL core specification, Datasheet
- Synthesis scripts
- Example application
- Technical support: IP Core implementation support, 3 months maintenance, Delivery the IP Core updates, minor and major versions changes, Delivery the documentation updates, Phone & email support



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