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 Digital Core Design 
Part Number : D32PRO
Short Desc. : Royalty-free and fully scalable 32-bit RISC CPU
Overview :

The D32PRO is a royalty-free, silicon proven, high performance soft core of a single-chip 32-bit embedded controller, with Floating Point Coprocessor.

 

Thanks to its increased code density, the D32PRO meets power and size requirements of new connected devices. That’s why both power and performance of this IP Core predestine it as a real alternative for ARM Cortex M0/M0+/M1/M3 in the deeply embedded market and especially for emerging market of connected devices (IoT). Responding to continuing demands for less power drain in system-on-chip (SoC) designs, DCD has developed the instruction set aimed at reducing the size of system’s instruction memory. The D32PRO is aimed at low-power always on/always listening systems and those with less demanding clock frequencies such as Bluetooth Low Energy. Nevertheless the core is perfect for embedded systems that require greater computational performance and system complexity by supporting dual- and multi-core systems as well as improved code density. DCD’s IP Core is fully customizable – it is delivered in an exact configuration to meet your requirements. The D32PRO comes with wide variety of peripherals, like USB, SPI, LCD, HDLC, UART, Ethernet MAC, CAN, LIN, RTC and many more – ready to be implemented with the CPU. The D32PRO is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design.


Features : - Configurable 32-bit Harvard architecture
- Performance up to 1.52 / 2.67 DMIPS/MHz and 2.59 CoreMarks/MHz
- Small footprint starting at 10.6k/6.8k ASIC gates
- Very high clock frequency up to 1 GHz in modern ASIC technologies
- Fifteen 32-bit general Purpose registers
- ASIC Silicon proven architecture
- Up to 256 MB of Code Space with encrypted bootloader
- Up to 256 MB of Data Space
- Built-in configurable Floating Point co-processor using dedicated instructions
- Configurable 32-bit hardware multiplier
- Configurable 32-bit hardware divider
- Configurable 32-bit hardware shifter
- Low power consumption by Advanced Power Management Unit
- Advanced Power management mode
- Switchback feature
- Stop mode
- Configurable Interrupt Controller
- Non Maskable Interrupt
- Up to 16 priority levels
- Up to 32 external interrupt sources
- System clock controller supporting
- Phase Locked Loops (PLL)
- external clock generator
- on-chip clock oscillator
- DoCD™ on-chip debug unit
- Processor execution control
- Run, Halt
- Step into instruction
- Skip instruction
- Read-write all processor contents
- System Space
- Program Memory Space
- Data Memory Space
- Peripherals Space
- Code execution breakpoints
- up to eight real-time PC breakpoints
- unlimited number of real-time OPCODE breakpoints
- Hardware execution watchpoints at
- Data Memory Space
- Program Memory Space
- Peripherals Space
- System Space
- Hardware watchpoints activated at a certain
- address by any write into any Space
- address by any read from Space
- address by write into space a required data
- address by read from space a required data
- Hardware watchpoint windows activated at a certain
- Start/stop address by any write into any Space
- Start/stop address by any read from Space
- Start/stop address by write into space a required data
- Start/stop address by read from space a required data
- 2-wire high-speed communication interface
- Ultimate dense code
- Great variety of peripherals
- AHB-Lite interface ready
- Rapid & easy development with ready to use tools
- Customization friendly with GUI
- Patent pending architecture
- Royalty-free
Categories :
Tags : 32-bit RISC RISC-V
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria 10
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
ARRIA V GZ
ARRIA V ST
ARRIA V SX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
EP5C
FLEX 10K
HardCopy
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
HardCopy Stratix
MAX II
MAX V
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
STRATIX III E
Stratix IV
STRATIX IV E
STRATIX IV GT
STRATIX IV GX
Stratix V
STRATIX V E
STRATIX V GS
STRATIX V GT
STRATIX V GX
Lattice :
ispClock
ispMACH 4000
LatticeEC/ECP
LatticeECP2
LatticeECP2M
LatticeECP3
LatticeSC
LatticeSCM
LatticeXP
LatticeXP2
MachXO
MachXO2
Platform Manager
Power Manager II
Xilinx :
Artix-7
Kintex-7
Kintex-7 -2L
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type : Soft
Deliverables : - The list of deliverables consists of:
- ASIC proven architecture
- Source code:
- VERILOG Source Code or
- FPGA Netlist
- VERILOG test bench environment
- ModelSim automatic simulation macros
- NCSim automatic simulation macros
- Tests with reference responses
- Technical documentation
- Installation notes
- HDL core specification
- Datasheet
- Synthesis scripts
- Example application
- Technical support
- IP Core implementation support
- 3 months maintenance
- Delivery of the IP Core and documentation updates, minor and major versions changes
- Phone & email support
TrueCircuits:



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