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 Digital Core Design 
Part Number : DI3CM-FIFO
Short Desc. : Master I3C bus controller with FIFO
Overview :

The DI3CM-FIFO Core incorporates all features required by the latest MIPI I3C specification.

The I3C (Improved Inter Integrated Circuit) is the next generation from I2C. Keeping the best assets from its elder brother, the I3C has major improvements in use and power and performance. The Core uses just two pins and consumes a fraction of the energy, reducing cost and complexity while allowing multiple sensors from different vendors to be easily interfaced to a controller or application processor.

Digital Core Design maintains backward compatibility, to enable a smooth transition from I2C to I3C and focus on simple implementation. The newest Core offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems. The same I3C standardizes sensor communication, reduces the number of physical pins used in sensor system integration and supports low-power, high-speed and other critical features that are currently covered by I2C and SPI.


Features : - Conforms to MIPI I3C v1.0 specifications
- MIPI Manufacturer ID: 0x03B3
- Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
- Legacy I2C messaging
- I2C-like Single Data Rate messaging (SDR)
- Master operation with FIFO:
- Master transmitter
- Master receiver
- Supports flexible transmission speed modes:
- FAST-PLUS (up to 1000 kb/s)
- SDR (up to 12,5 Mb/s)
- Configurable FIFO size up to 256 Bytes
- Configurable SDA/SCL glitch filter
- Software programmable SDA/SCL bus timings
- Multi-master systems supported
- Interrupt generation
- Allows operation from a wide range of input clock frequencies (build-in 12-bit clock timer)
- Configurable interface allows easy connection to standard bus interfaces: APB, AHB, 8051, 80251, others
- Support for in-band interrupts
- Support for I3C common command codes
- Dynamic address assignment (DAA) support
- Command queue support
- Low power management support
- Fully interoperable with third-party I3C master and slave solutions
- Fully synthesizable, static synchronous design with positive edge clocking and synchronous reset
Categories :
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria 10
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
ARRIA V GZ
ARRIA V ST
ARRIA V SX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
EP5C
FLEX 10K
HardCopy
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
HardCopy Stratix
MAX II
MAX V
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
STRATIX III E
Stratix IV
STRATIX IV E
STRATIX IV GT
STRATIX IV GX
Stratix V
STRATIX V E
STRATIX V GS
STRATIX V GT
STRATIX V GX
Lattice :
ispClock
ispMACH 4000
LatticeEC/ECP
LatticeECP2
LatticeECP2M
LatticeECP3
LatticeSC
LatticeSCM
LatticeXP
LatticeXP2
MachXO
MachXO2
Platform Manager
Power Manager II
Xilinx :
Artix-7
Kintex-7
Kintex-7 -2L
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type : Soft
Deliverables : - Source code:
- VERILOG or VHDL Source Code
- VERILOG or VHDL test bench environment
- Active-HDL automatic simulation macros
- ModelSim automatic simulation macros
- Tests with reference responses
- Technical documentation
- Installation notes
- HDL core specification
- Datasheet
- Synthesis scripts
- Example application
- Netlist
- Netlist for selected FPGA family
- Sample FPGA project
- Technical documentation
- HDL core specification
- Datasheet
- Technical support
- IP Core implementation
- 3 months maintenance
- Delivery of the IP Core and documentation
- updates, minor and major versions changes
- Phone & email support



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