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 Digital Core Design 
Part Number : DFPSQRT
Overview :

The DFPSQRT uses the pipelined mathematics algorithm to compute square root function. The input number format is accord-ing to IEEE-754 standard. DFPSQRT sup-ports single precision real numbers. SQRT operation can be pipelined up to 9 levels. Input data are fed every clock cycle. The first result appears after 9 clock periods latency and next results are available each clock cycle. Precision and accuracy are parameter-ized.


Features : - Full IEEE-754 compliance
- Single precision real format support
- Simple interface
- No programming required
- 9 levels pipelining
- 24-bit accuracy, 6 fractional decimal digits
- Results available at every clock
- Fully configurable
Categories :
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria GX
Arria II GX
Cyclone
Cyclone II
Cyclone III
FLEX 10K
HardCopy
HardCopy II
HardCopy Stratix
MAX II
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
Stratix IV
Lattice :
ispClock
ispMACH 4000
LatticeEC/ECP
LatticeECP2
LatticeECP2M
LatticeECP3
LatticeSC
LatticeSCM
LatticeXP
LatticeXP2
MachXO
MachXO2
Platform Manager
Power Manager II
Xilinx :
Artix-7
Kintex-7
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type : Soft
Deliverables : - Source code: VHDL Source Code or/and VERILOG Source Code or/and FPGA Netlist
- VHDL & VERILOG test bench environment: Active HDL automatic simulation macros, ModelSim automatic simulation macros, NCSim automatic simulation macros, Tests with reference responses
- Technical documentation: Installation notes, HDL core specification, Datasheet
- Synthesis scripts
- Example application
- Technical support: IP Core implementation support, 3 months maintenance, Delivery the IP Core updates, minor and major versions changes, Delivery the documentation updates, Phone & email support



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