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 Digital Core Design 
Part Number : DFPMU-DP
Overview :

DFPMU-DP is a Floating Point Coprocessor, designed to assist CPU in performing the floating point mathematic computations. DFPMU-DP directly replaces C software functions, by equivalent, very fast hardware operations, which significantly accelerate system performance. It doesn’t require any programming,


Features : - Configurability of all available functions
- C interface supplied for all popular compilers: GNU C/C++, 8051 compilers
- No programming required
- IEEE-754 Double precision real format support – double type
- IEEE-754 Single precision real format support – float type
- 8-bit, 16-bit 32-bit and 52-bit integers for-mat supported – integer types
- Flexible arguments and result registers location
- Performs the following functions:
- FADD, FSUB – addition, subtraction
- FMUL, FDIV – multiplication, division
- FSQRT – square root
- FXAM – examine input data
- FUCOM – comparison
- FTAN – tangent
- FATAN – arctangent
- FCLD, FILD – 8-bit, 16-bit integer to dou-ble
- FLLD, FELD – 32-bit, 52-bit integer to double
- FCST, FIST – double to 8-bit, 16-bi inte-ger
- FLST, FEST – double to 32-bit, 52-bit in-teger
- FFLD – float to double
- FFST – double to float
- Exceptions built-in routines
- Masks each exception indicator:
- Precision lack PE
- Underflow result UE
- Overflow result OE
- Invalid operand IE
- Division by zero ZE
- Denormal operand DE
Categories :
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria GX
Arria II GX
Cyclone
Cyclone II
Cyclone III
FLEX 10K
HardCopy
HardCopy II
HardCopy Stratix
MAX II
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
Stratix IV
Lattice :
ispClock
ispMACH 4000
LatticeEC/ECP
LatticeECP2
LatticeECP2M
LatticeECP3
LatticeSC
LatticeSCM
LatticeXP
LatticeXP2
MachXO
MachXO2
Platform Manager
Power Manager II
Xilinx :
Artix-7
Kintex-7
Kintex-7 -2L
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type : Soft
Deliverables : - Source code: VHDL Source Code or/and VERILOG Source Code or/and FPGA Netlist
- VHDL & VERILOG test bench environment: Active HDL automatic simulation macros, ModelSim automatic simulation macros, NCSim automatic simulation macros, Tests with reference responses
- Technical documentation: Installation notes, HDL core specification, Datasheet
- Synthesis scripts
- Example application
- Technical support: IP Core implementation support, 3 months maintenance, Delivery the IP Core updates, minor and major versions changes, Delivery the documentation updates, Phone & email support



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