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 Digital Core Design 
Part Number : DMAC
Overview :

Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. The DMAC-RMII, in cooperation with external PHY device, enables network functionality in design. It is able to transmit and receive Ethernet frames to and from the network. Half and full duplex modes are supported, as well as 10 and 100 Mbit/s speed. The Core can work with wide range of processors: 816 and 32 bit data bus, either little or big endian byte order format. The DMAC-RMII provides static configuration of PHY IC. Please remember that our design is technology independent and thus can be implemented in variety of process technologies. This Core strictly conforms to the IEEE 802.3 standard.


Features : - Conforms to IEEE 802.3-2002 specification
- Configurable width CPU interface with little or big endianess:
- 8-bit
- 16-bit
- 32-bit
- Simple interface allows easy connection to CPU
- Narrow address bus (4 bits) with indirect I/O interface for transmitted and received data dual port memories
- Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs
- Reduced Media Independent Interface (RMII) for connection to external 10/100 Mbps PHY transceivers
- Supports full and half duplex operation at 10 Mbps or 100 Mbps
- CRC-32 algorithm:
- calculates the FCS nibble at a time
- automatic FCS generation and checking
- able to capture frames with CRC errors if required
- Dynamic PHY configuration by STA management interface
- Early receive and transmit interrupts to increase data throughput
- Programmable MAC address
- Promiscuous mode support
- Allows operation from a wide range of input bus clock frequencies
- Fully synthesizable
- Static synchronous design
- Positive edge clocking
- No internal tri-states
- Lite design, small gate count and fast operation
- Scan test ready
Categories :
Maturity : 10+
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria 10
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
ARRIA V GZ
ARRIA V ST
ARRIA V SX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
EP5C
FLEX 10K
HardCopy
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
HardCopy Stratix
MAX II
MAX V
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
STRATIX III E
Stratix IV
STRATIX IV E
STRATIX IV GT
STRATIX IV GX
Stratix V
STRATIX V E
STRATIX V GS
STRATIX V GT
STRATIX V GX
Lattice :
ispClock
ispMACH 4000
LatticeEC/ECP
LatticeECP2
LatticeECP2M
LatticeECP3
LatticeSC
LatticeSCM
LatticeXP
LatticeXP2
MachXO
MachXO2
Platform Manager
Power Manager II
Xilinx :
Artix-7
Kintex-7
Kintex-7 -2L
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type : Soft
Deliverables : - Source code: VHDL Source Code or/and VERILOG Source Code or/and FPGA Netlist
- VHDL & VERILOG test bench environment: Active HDL automatic simulation macros, ModelSim automatic simulation macros, NCSim automatic simulation macros, Tests with reference responses
- Technical documentation: Installation notes, HDL core specification, Datasheet
- Synthesis scripts
- Example application
- Technical support: IP Core implementation support, 3 months maintenance, Delivery the IP Core updates, minor and major versions changes, Delivery the documentation updates, Phone & email support



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