Barco Silex 
Part Number : BA119JPEGCOD
Overview :
The JPEG codec core is intended for high-speed encoding and decoding of gray-scale, color or multi-scan images according to the ISO/IEC 10918-1 baseline-coding standard. The codec supports all features of the baseline standard, including restart markers, DNL, user-definable comments and application markers. In decoding mode it performs stand-alone full header parsing. It is able to encode and decode abbreviated-format or full-format images, automatically extracting the quantization and entropy tables in decoding mode and automatically generating the fixed-length headers from its internal user-programmable header memory in encoding mode.
Features : - Half duplex JPEG codec
- High-speed sustained single clock cycle per pixel component encoding and decoding
- Single clock cycle Huffman decoding and encoding
- 100% baseline ISO/IEC 10918-1 JPEG compliance for color images (single and multi-scan formats) extending to effective 255-scan support.
- Full header generation capability with default pre-programmed Huffman and quantization tables or user-definable custom tables in encoding mode.
- Full header parsing capability and automatic on-the-fly Huffman and quantization tables reprogramming from header data in decoding mode,
- One-pass encoding scheme with compression ratio regulation.
- Header error catching features
- Full baseline JPEG format and abbreviated format support, including restart markers and DNL.
- Simple FIFO interfaces for compressed data (32 bit) and pixel interface (8 bit)
- Simple CPU interface for codec control and programming.
- Easy-to-use status and control interface through 21 internal registers.
- Programmable external interrupts for event follow-up.
- For entropy tables (two DC, two AC), four quantization tables.
- Burst image-sequence encoding support for images with identical tables and color format.
- Burst image-sequence decoding support for images with identical tables.
- 8-bit/pixel components.
- 8x8 block format pixel interface with classical scan order (row by row from left to right).
- Fully synchronous hardware design.
- Fully stallable compressed dat-interface, stallable pixel interface on a block-by-block basis.
- Throughputs ranging from sub CIF 25Hz to SDTV to HDTV1280x720 50Hz
Categories :
Portability :
Type : Soft
Deliverables : - RTL Code or netlist (depending on license type), Functional simulation testbench, Synthesis script, Full documentation

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