austriamicrosystems AG 
Short Desc. : Single Port RAM in 0.8 µm CMOS
Overview :
The SPRAM compiler system enables automatic generation of single port RAM blocks for the configurations shown above. All representations are available for a complete design flow as symbol, simulation models, and GDSII layout data. The compiler system is not included in the HIT-Kit. Memories are provided on reques
Features : - Memory Compiler for Single Port RAM in following CMOS Technologies:
- 0.8 µm BYx - compatible with CMOS parts of the process
- 0.8 µm CXx - compatible with 5.0V CMOS parts of CXZ
- 16,384 bit maximum memory size
- 1 .. 32 bits per word
- 32 .. 16,384 words per RAM
- one data bus or separated data buses for data input/output
- dataout with tri-state condition
- memory organisation in 1 or 2 memory banks
- several length/height ratios available (depending on total size)
Categories :
Portability :
Type : Soft
Deliverables : - cell library with symbol, functional, abstract and msps view, TLF 3.0 timing data file, black box description in ASCII format, GDSII data
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