|The A2MMU is an x86 compatible Memory Management Unit designed to support CPUs that require a full virtual memory system. The A2MMU uses a TLB cache mechanism to convert addresses from virtual to physical and also provides an autonomous Table walk mechanism to derive new address translations on TLB cache misses. This approach unloads the host CPU from having to support exception processing for all MMU functions. The CPU is only responsible for loading the primary table descriptors in supervisor mode. The A2MMU may be configured as a dual TLB system to support Harvard architecture machines with separate instruction and data paths.