Short Desc. : OPB IPIF
Overview :
The OPB IPIF architecture specification facilitates the connection of Xilinx or customer IP modules to the IBM On-Chip Peripheral Bus (OPB). The OPB is part of IBM's CoreConnect™ family of data buses and associated infrastructure. CoreConnect is intended for use in system-on-chip environments, including XIlinx Virtex-II Pro™ FPGAs with embedded PowerPC™ hard processors and FPGAs using the MicroBlaze™ soft processor. This IP core is one of more than 20 IP cores that are part of the Embedded Development Kit.
Features : - Compatible with IBM CoreConnect 32-bit OPB.
- Supports user IP data widths from 8 bits to 32 bits with automatic byte steering.
- Extensive user customizing support via HDL parameterization. user optioned services include:
- Local IP Interrupt collection with user S/W programmable enables/disables.
- user S/W triggered reset generator for localized reset of user’s core.
- Sequential-Address transfer support.
- user configured WrFIFO with optional IP packet support.
- user configured RdFIFO with optional IP packet support.
Categories :
Portability :
Type : Soft

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