Part Number : Accumulator
Overview :
The Accumulator IP core generates adder-, subtractor-, and adder/subtractor-based accumulators operating on signed or unsigned input. Data is entered on Port B. An alternate option allows the value of Port B being set to a constant. Carry input and carry/borrow/overflow options are also available. The range of inputs is from 1 to 64 bits wide and outputs from 1 to 66 and the module supports user-programmable feedback scaling.
Features : - Drop-in module for Virtex™, Virtex-E, Virtex-II, Virtex-II Pro, Virtex-4, Spartan™-II, Spartan-IIE, Spartan-3, and Spartan-3E FPGAs
- Generates Add, Subtract, and Add/Subtract-based accumulators
- Supports two’s complement signed and unsigned operations
- Supports inputs ranging from 1 to 256 bits wide
- Supports outputs ranging from 1 to 258 bits wide
- User programmable feedback scaling
- Optional clock enable, asynchronous, and synchronous controls
- Optional nonregistered output
- Optional Bypass (Load) capability
- Uses relationally placed macro (RPM) mapping and placement technology for maximum and predictable performance
- Incorporates Xilinx Smart-IP™ technology for utmost parameterization and optimum implementation
- For use with v7.1i and later of the Xilinx CORE Generator™ system
Categories :
Portability :
Type : Soft

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