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Short Desc. :
PCI-HB -- 32-bit/33,66Mhz PCI Host Bridge Core
The PCI Host Bridge core enables data transfers between a host processor system and PCI bus based devices. The bridge is in charge of PCI bus arbitration, generating PCI clock and reset signals. An important part of the bridge is the bus arbiter.
The PCI-HB core is a generic core, which provides all the essential bridge functions without a host bus interface.
- PCI specification 2.3 compliant
- 33/66 MHz performance
- 32-bit datapath
- PCI reset generator
- PCI bus arbiter (up to 7 external bus agents)
- Interrupt controller
- Parity generation and parity error detection.
- Dual-port based shared memory
- PCI Configuration registers accessible from both PCI and host directions
- Available in synthesizable VHDL source code
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