Login

 Actel Corporation 
Part Number : MC-ACT-HDLC
Overview :
High-Level Data Link Control (HDLC) is bit-oriented and synchronous, and the most commonly used OSI Layer 2 protocol. Designed specifically for FPGA devices the MC-ACT-HDLC core provides the HDLC frame structure for OSI layer 2. The design is intended to be integrated with either FIFO or DMA memory, for both transmitting and receiving. The transmitter and receiver are independent blocks with separate clocks, allowing separate transmit and receive data rates. For more information or to obtain this core, please contact Avnet Engineering Services.
Features : - Conforms to International Standard ISO/IEC 3309 specification
- 16-bit/32-bit FCS generation and checking
- Flag and zero insertion and detection
- Full-duplex operation
- Synchronous operation
- Supports Actel's ProASICPLUS and Axcelerator families
- 28% Utilization in ProASICPLUS APA075 device
- 6% Utilization in Axcelerator AX500 device
Categories :
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise