Embedded, IP & SoC News
Submit New Event
Purchase Webinar Listing
Submit New Tutorial
Submit New Video
Submit New YouTube Video
Submit New Download
EDACafe Media Kit
Banner Ad Specifications
eMail Blast Specifications
VeriSilicon Holdings Co., Ltd.
Short Desc. :
The S13V25_CCP2RX _01 recovers a serial bit stream containing image data and converts it to a 4-bit 1/4 rate word. The receiver defined in this IP is only required to interface with the image sensor. The receiver consists of two LVDS receiver cells (Strobe and Data) followed by a 1:4 de-serializer. Only Data-Strobe mode needs to be supported in this design. Therefore the clock may always be recovered using a DDR Flop clocked by the XOR of Strobe and Data. In addition, only Sub-LVDS electrical requirements must be met.
- Sub-low voltage differential signaling input: VID = 25mV MIN.
- Converts the subLVDS strobe/data (up to 960 Mbps throughput bandwidth) back into parallel 4 bits of CMOS data/strobe
- Power-down control function
- Full industrial operating temperature range -40 ~ +125 C
- SMIC 0.13um Logic Salicide Process (1p6m, 1.2V/2.5V)
- On chip 100ohm resistance between receivers?each positive input and negative input
- Positive clock edge with data output
Analog & Mixed Signal
© 2020 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 —
, or visit our other sites: