||- User-specified connection map, address map, command map, and optional features.
- Configurable to provide a full or partial cross-bar topology.
- Flexible internal pipelining makes frequency independent of span.
- Configurable data path widths (sockets and internal) 16, 32, or 64 bits. Four to one range of widths allowed within any instance.
- Supports 1 cycle minimum latency paths.
- Permits clock rates of up to 250 Mhz subject to configuration choices in 90nm libraries.
- Configurable address widths up to 40 bits.
- Target decoding down to a granularity of 1 KB.
- Supports initiator sideband signaling for interrupts, errors, and power controls.
- Controls bandwidth and latency for each target core’s threads.
- Protects cores or memory regions from access by specific initiating cores or