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 CAST, Inc. 
Short Desc. : PCI-DHB-AHB - AMBA AHB Device/Host Bridge Core
Overview :

This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices.

The bridge supports Host Mode and Device Mode (selected by a dedicated input pin). In Host Mode, the bridge is in charge of PCI bus arbitration and generating the PCI reset signal. In Device Mode, the bridge implements a PCI target enabling PCI access to the AMBA AHB bus space behind the bridge.

The bridge enables higher utilization of the bus’ available bandwidth by prefetching PCI data and buffering AHB data, and allows the host to initiate PCI accesses or to respond to transactions initiated by other PCI devices.

The core complies with the PCI bus specification versions 3.0 and 2.3, and can act as a PCI master and target. Furthermore if implements PCI bus arbitration, supporting up to seven PCI bus agents, PCI reset signal generation, and all types of PCI transactions provisioned by the standard.
The host connects to the bridge via master and a slave 32-bit AMBA/AHB bus interfaces. The AHB slave interface allows the host to access the status and to control registers and initiate PCI Transfers, while data from the PCI target is communicated to the host via the AHB master interface.

The PCI-DHB-AHB builds on more than 10 years of CAST PCI IP expertise and has been designed for straightforward reuse, with proven design practices that ensure easy integration and smooth technology mapping. The core is available in synthesizable RTL or as a targeted FPGA netlist, and is delivered with everything required for rapid and successful integration and implementation.


Features : - PCI Device/Host Bridge
- Pin-selectable PCI Host Bridge or PCI Device operation
- Enables data communication between the Host Processor residing on an AHB bus and devices on the PCI bus
- PCI I/O space and memory space are mapped directly to the AMBA AHB memory space
- PCI Interrupt and System Errors are propagated as interrupts to the host
- PCI Configuration registers are accessible from both PCI and host directions
- Advanced PCI data prefetching and AHB data buffering for improved bus bandwidth utilization
- Asynchronous AMBA/AHB and PCI clocks
- PCI Interface
- PCI specification 3.0 and 2.3 compliant
- 33/66 MHz
- 32-bit bus width
- 32-bit address space
- Parity generation and parity error detection
- PCI Master & Target and Device support all types of transactions:
- Configuration space read/write
- Memory space read/write
- I/O Space read/write
- Interrupt acknowledge (optional)
- Special cycles (optional)
- PCI reset generator
- PCI bus arbiter
- Up to 7 external bus agents
- Flexible priority schemes
- Agent malfunction detection and reporting
- AHB Interface
- 32-bit AMBA/AHB v2.0 host interface
- AHB Slave enables host to initiated PCI transaction and access configuration registers
- AHB Master delivers data from the PCI target interface to the host
Categories :
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria 10
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
ARRIA V GZ
ARRIA V ST
ARRIA V SX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
EP5C
FLEX 10K
HardCopy
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
HardCopy Stratix
MAX II
MAX V
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
STRATIX III E
Stratix IV
STRATIX IV E
STRATIX IV GT
STRATIX IV GX
Stratix V
STRATIX V E
STRATIX V GS
STRATIX V GT
STRATIX V GX
Lattice :
ispClock
ispMACH 4000
LatticeEC/ECP
LatticeECP2
LatticeECP2M
LatticeECP3
LatticeSC
LatticeSCM
LatticeXP
LatticeXP2
MachXO
MachXO2
Platform Manager
Power Manager II
Xilinx :
Artix-7
Kintex-7
Kintex-7 -2L
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type : Soft
Deliverables : - HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs) Sophisticated HDL Testbench, Simulation and Synthesis Scripts, Documentation
Verific: SystemVerilog & VHDL Parsers



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