True Circuits 
Part Number : TCI-TN55GP-DSMPLL
Short Desc. : TSMC CLN55GP 55nm Deskew PLL - 260MHz-1300MHz
Features : - Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
Categories :
Tags : Deskew PLL, TSMC 55nm GP, TSMC CLN55GP, TSMC, CLN55GP , Low Jitter
Maturity : Silicon proven
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

Deliverables : - GDSII (100% DRC and LVS clean)
- LVS Spice netlist
- Verilog model
- Synopsys synthesis model
- LEF for clock generator PLL
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers

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