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 True Circuits 
Part Number : TCI-UL55LP-DSMPLL
Short Desc. : UMC L55LP 55nm Deskew PLL - 120MHz-600MHz
Features : - Designed to eliminate clock distribution latency in systems and individual chips.
- Precisely aligns the clock distribution output with a reference clock.
- Provides a zero-delay feedback divider and zero-skew divided clock outputs.
Categories :
Tags : Deskew PLL, UMC 55nm LP, UMC L55LP, UMC, L55LP , Low Jitter
Maturity : Silicon proven
Portability :
Type :
 Hard IP 
Foundry :
UMC
Nodes :
55nm
Process :
L55LP

Deliverables : - GDSII (100% DRC and LVS clean)
- LVS Spice netlist
- Verilog model
- Synopsys synthesis model
- LEF for clock generator PLL



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