Verification Methodology Manual for Low Power
by Srikanth Jadcherla , Janick Bergeron , Yoshio Inoue , David Flynn



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Power management is now the biggest barrier to the continuation of Moore s law, and low power IC designs have introduced new classes of bugs and silicon failures. As a result, successful verification of low power designs has an immense impact on the overall success of a product. Today s verification tools have evolved to detect these bugs as early as at the RTL design stage, which reduces the risk of field failures. However, tools alone are not sufficient. A rigorous verification methodology for low power is the correct prescription for avoiding unpleasant and costly surprises.

Leveraging years of collective industry best practices, the Verification Methodology Manual for Low Power (VMM-LP) introduces a new verification methodology for low power and provides a blueprint for successful verification of low power designs. It describes the common causes of low power design failures, the impact of low power on the specification of power intent, the implementation of test plans, the setup of testbenches and the metrics of verification using assertions and coverage. The VMM-LP builds on the base classes in industry standard VMM to enable the deployment of a consistent, reusable, and scalable power-aware verification environment across multiple design projects within a company. In addition to benefitting from the extensive practical experience of the authors from ARM, Synopsys, and Renesas, the VMM-LP is also peer-reviewed by more than 30 low power design and verification experts from around the world.



Book Details
  • Media : Paperback
  • Publisher : Synopsys (February 18, 2009)
  • Language : English
  • ISBN : 160743413X
  • Amazon.com Sales Rank : # 4,275,116 in Amazon.com Books Sales

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