Sizing the Design - Selecting the Array
Last Edit July 22, 2001
Drivers
Special driver macros may be provided in a library. These "super-drivers"
are not derated. They are designed to provide a clean edge even when loaded
to their rated limit. These drivers will use more current and more cells
then the non-driver but fewer of them are required to drive the same load.
The result may be the same cell utilization and the same power.
Another feature of drivers should be considered. When timing analysis
is performed, the super-drivers and drivers will be seen to have a lower
k-factor (drive factor) than the non-driver macros, resulting in lower
inter-macro delays for the same load than a non-driver macro could provide.
Drivers may be interface macros or internal macros.
Hook-up or interconnect restrictions
Hook-up is used here to define the rules on grounding an input pin to
a macro. CMOS and BiCMOS technologies require that all unused macro input
pins (non-primary array inputs) be clipped to VDD or VSS, no exceptions.
Bipolar technologies allow the unused input pins to be tied to global
ground. The ground symbol on the schematic is for human comprehension
and to allow checking software to understand that the designer meant to
leave the pin unattached.
For some arrays, a macro input pin connected to global ground on a schematic
will mean that the pin "floats", or is unattached to anything
when silicon is built. For others, these pins are physically attached
to a confirmed logical low by connecting to a rail (CMOS) or by strapping
the base to the emitter (bipolar) through conditional geometry.
For the Q20000 Series these pins are base input to transistors and when
unused are tied to the emitter to ensure a logical low. For the Q5000
Series, the pins were allowed to float.
Whether or not the pins are allowed to float, there will be cases where
specific macro pins are restricted, i.e., these pins cannot be attached
to global ground but must be driven low by another macro. This is a hook-up
restriction.
When hook-up restrictions exist, some macro must be added to the schematic
to drive these pins low (or high). The number added will depend on the
number of loads that must be driven low or high.
Pin restrictions - interconnect restrictions
Some macros are pin-restricted in that they may not be freely connected
to any other macro but much be driven by or drive a specific class of
macro. As an example, TTL three-state outputs and TTL bidirectional macros
in some macro libraries must have their enable pins driven by a macro
known as a three-state enable driver. No other macro may drive that enable
pin. The three-state enable drivers can only be connected to drive these
specific pins; they may not be used to drive other macros.
In the Q5000 library, three-state enable drivers may only be placed on
interface I/O cells, even when they are driven by internal signals, leaving
the pad unused in this case.
When pin-restrictions cause the use of specific macros and these macros
have re stricted placements, the impact on cell utilization must be considered.
Internal cell utilization
When the paths have all been checked for fan-out, pin restrictions, hook-up
restric tions, placement rules, etc., the internal cell utilization can
be estimated. As stated in Chapter 2, this is the sum of all the internal
cells used divided by the number of internal cells available.
Internal cell utilization = (number of internal cells used by the
circuit) / (number of internal cells available on the array)
Further changes
Other factors that can change the estimated cell utilization include
adjustments made for power reduction, for speed enhancement, or for cell
utilization reduction for ei ther interface or internal cells.
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