Power Considerations
Last Edit July 22, 2001
Power Reduction Techniques
Regardless of the array technology, items whose use will increase the
power dissipated by the array should be carefully chosen. A tradeoff or
balance of different design objectives should reflect judicious selections
that maintain speed while keeping power dissipation to a minimum and circuit
size within the array constraints. Power considerations are no less serious
for the large CMOS and BiCMOS arrays.
Table 7-8 summarizes the design choices that contribute to higher
power; which choices are possible depends on the array series.
Table 7-8 Power Dissipation Contributors
Contributors to Power Dissipation |
- High-speed macro options
propagation delay - faster
- High fan-out macro options
low distortion
propagation delay - may be faster
- Driver macros (clock drivers)
chip-efficient
low distortion
propagation delay - may be faster
- Multi-cell macros
chip-efficient
lower cell count
propagation delay - may be faster
- Unused outputs
- Powered-down unused outputs
- Unused inputs
|
Table 7-9 summarizes the choices that can be made to reduce power
and the design tradeoffs that these may require.
Table 7-9 Low Power Options
Low Power Dissipation |
Tradeoff |
Low-power macro options |
higher propagation delay
distortionless drive (maybe)
higher distortion drive (maybe) |
Placement of I/O to reduce bias
or overhead current |
less flexibility in placement;
less performance (maybe) |
|