|
Power Considerations
Last Edit July 22, 2001
Computing DC Power Dissipation
To compute the worst-case DC power for a non-CMOS circuit, perform the following
steps. There will be some variation in the complexity of the steps between
vendors, depending on the method used to specify current or power dissipation
for individual macros.
Steps To Compute Maximum Worst-Case DC Power
The following example methodology assumes that typical current is specified.
It applies to any power-supply configuration
- Sum all individual interface macro currents and multiply by the interface
macro worst-case current multiplier. Keep IEE and ICC separate
- Sum all individual internal macro currents and multiply by the internal
macro worst-case current multiplier. Keep IEE and ICC separate. Skip
this step for the BiCMOS arrays
- Find the IEE and ICC overhead currents and multiply them by the worst-case
overhead current multiplier. Keep IEE and ICC separate
- Add all IEE currents together
- Add all ICC currents together
- Find the worst-case VCC and VEE voltages
- Multiply IEE * VEE
- Multiply ICC * VCC
- Compute ECL static power dissipation:
1.3 * termination current * number of outputs.
Adjust the equation when the standard assumptions are not met
- Add all items together. This is the worst-case maximum DC power dissipated
by the circuit if it is bipolar. It is the interface macro worst-case
maximum DC power if the circuit is for the BiCMOS arrays
Reduction for single-supply circuits
There is an obvious reduction in the complexity of the steps if the circuit
uses only one power supply. Under this condition, IEE becomes ICC when
a +5V reference circuit is being analyzed. There is no ICC in a -5.2V
or -4.5V single-supply circuit
Table 7-11 Currents Present By I/O Mode
Power Supply |
Technology |
Compute IEE |
Compute ICC |
SINGLE, +5V |
100% TTL |
- |
X |
SINGLE, +5V |
100% ECL |
- |
X |
SINGLE, +5V |
ECL/TTL |
- |
X |
SINGLE, -5.2V |
100% ECL |
X |
- |
SINGLE, -4.5V |
100% ECL |
X |
- |
DUAL, +5V -5.2V |
100% ECL |
X |
- |
DUAL, +5V -5.2V |
ECL/TTL |
X |
X |
DUAL, +5V -4.5V |
100% ECL |
X |
- |
DUAL, +5V -4.5V |
ECL/TTL |
X |
X |
The unusual dual-supply 100% ECL circuits (DECL) shown in Table 7-11
are required for minimum cell 25 ohm terminations (see the AMCC Q20000
Series Darlingtons)
|