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| 1 |
IP REUSE IN ADDRESSING THE NEED FOR INCREASED VLSI DESIGN PRODUCTIVITY |
| 1.1 |
Some General Observations About VLSI Chips |
| 1.1.1 |
Some Major Challenges in VLSI Chip Design |
| 1.1.2 |
Design Issues for Pre-DSM Technologies |
| 1.1.3 |
Design Issues for DSM Technologies |
| 1.1.4 |
Going From Pre-DSM to DSM Requires Changes |
| 1.1.5 |
The Concept of Hard IP Reuse |
| 1.1.6 |
With Hard IP Migration, Only Some Circuit Properties Change |
| 1.2 |
Economics Considerations for Bigger, Faster, More Complex
Chips? |
| 1.2.1 |
Economics by Saving on Simulation and Testing Through IP Reuse |
| 1.2.2 |
IP Reuse to Keep Pace with Processing Technology Advances |
| 1.2.3 |
The Challenge of Filling Fabs for Profitability |
| 1.2.4 |
Planning in the Face of Uncertainties. |
| 1.3 |
A Preview of Areas of Hard IP Engineering |
| 1.3.1 |
Hard IP Retargeting and Designing for DSM Technologies and
Yield |
| 1.3.2 |
IP Reuse and the Front-End/Back-End Connection |
| 1.3.3 |
IP Reuse for a System-on-Chip (S-o-C) |
| 1.3.4 |
An Ultimate Mix and Match S-o-C Methodology |
| 1.3.5 |
Productive Hard IP Creation |
| 1.4 |
Barriers to and Limitations of Hard IP Reuse |
| 1.4.1 |
Problems With Attitude |
| 1.4.2 |
Problems With Infrastructure |
| 1.4.3 |
Fundamental Technical Limitations |
| 1.4.4 |
Summary of Conclusions |
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