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2 |
HARD IP MIGRATION WITH A PROVEN SYSTEM AND METHODOLOGY |
2.1 |
Hard IP Reuse, Linear Shrink or Compaction? |
2.1.1 |
Keeping What’s Good / Improving the Rest |
2.1.2 |
Layout Flexibility and Control with Polygon Based Compaction |
2.1.3 |
Linear Shrink Versus Compaction |
2.2 |
Retargeting to a New Process with Compaction |
2.2.1 |
Retargeting for Unchanged Functionality |
2.2.2 |
Retargeting to Conform to Target Process Design Rules |
2.2.3 |
Retargeting for Reliability |
2.3 |
Correct Electrical and Timing Behavior of Migrated Chips |
2.3.1 |
Retargeting for Correct Interconnect Timing |
2.3.2 |
Retargeting for Correct Transistor Timing |
2.3.3 |
Retargeting for Correct Interconnect and Transistor Timing |
2.4 |
Inputs, Feedback and Leverage on the Layout |
2.4.1 |
Setup for Migration Process |
2.4.2 |
A Bird’s Eye View of a Migration |
2.4.3 |
Output Data (Feedback) From the Compactor |
2.4.4 |
Statistical Feedback on the Layout |
2.4.5 |
Keeping Polygons Edges on a Grid |
2.4.6 |
Compaction-Induced Jogging |
2.4.7 |
Contact Optimization After Migration |
2.4.8 |
Minimization of Parasitic Capacitance or Resistance |
2.4.9 |
Some Other Challenges |
2.4.10 |
Summary on Compaction |
2.5 |
Evolution and Applications of Hard IP Migration Methodology |
2.5.1 |
Standard Cell Library Migration |
2.5.2 |
Migration of Regular Structures |
2.5.3 |
Hierarchy Maintenance in Hard IP Migration |
2.5.4 |
Flat Hard IP Migration |
2.5.5 |
Migration of Entire Chips |
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