All Categories : Technical Presentations Bookmark and Share

Title : eASIC reduces multi-level package design times with CST MICROWAVE STUDIO
Company : CST - Computer Simulation Technology
File Name : CST-successstory-eASIC-web-edacafe.pdf
Size : 426865
Type : application/pdf
Date : 23-Jan-2014
Downloads : 2

Rate This File
5 Stars
4 Stars
3 Stars
2 Stars
1 Star

When designing a chip for a high-speed application, the whole channel, including the package and the printed circuit board affects the performance. Find out how multi-level package design times can be reduced with the help of CST.
User Reviews More Reviews Review This File

Aldec

Jobs
Software Engineering Manager - DevOps for Xilinx at San Jose, California
Product Marketing Manager for MathWorks at Natick, Massachusetts
Staff Verification Engineer for Xilinx at San Jose, California
Upcoming Events
ASMC 2019 at Saratoga Springs City Center NY - May 6 - 9, 2019
Semicon Southeast Asia 2019 at Kuala Lumpur Malaysia - May 7 - 9, 2019
ASYNC 2019 at Art Hotel Hirosaki City the JR Hirosaki Station Hirosaki Japan - May 12 - 15, 2019
The ConFab 2019 at Las Vegas NV - May 14 - 17, 2019
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL



Internet Business Systems © 2019 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise