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Title : eASIC reduces multi-level package design times with CST MICROWAVE STUDIO
Company : CST - Computer Simulation Technology
File Name : CST-successstory-eASIC-web-edacafe.pdf
Size : 426865
Type : application/pdf
Date : 23-Jan-2014
Downloads : 2

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When designing a chip for a high-speed application, the whole channel, including the package and the printed circuit board affects the performance. Find out how multi-level package design times can be reduced with the help of CST.
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