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Title : HOW TO MINIMIZE DESIGN MARGINS WITH ACCURATE ADVANCED TRANSISTOR DEGRADATION MODELS
Company : Fraunhofer Institute for Integrated Circuits
File Name : wp_fraunhofer-eas_degradation.pdf
Size : 912194
Type : application/pdf
Date : 10-Nov-2017
Downloads : 12

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Reliability is a major criterion for integrated circuits (ICs) in safety critical applications, such as automotive, medical, or aviation electronics. A particular effect that contributes to wear-out is device (i.e. transistor) degradation. Its impact on the circuit behavior can be verified by circuit level aging simulations, which are offered by various EDA vendors. However, reasonable results can only be achieved with accurate and efficient device (i.e. transistor) degradation models. This white paper discusses the state of the art and points out opportunities for improvements.
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