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Title : Challenges and Requirements for Power-Aware Degug
Company : SpringSoft, Inc.
File Name : PowerAwareDebug_FINAL.pdf
Size : 374368
Type : application/pdf
Date : 11-Mar-2010
Downloads : 27

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Traditionally, area and timing have been the major issues faced by Integrated Circuit (IC) designers. Now, power has also emerged as a major concern for three reasons. First, low power is favored by numerous end‐applications, such as cellular phones, hand‐held gaming devices, and portable media players. Second, there is an increase in power density due to higher clock speeds and shrinking process geometries control. Last but not least, most system‐on‐chip (SoC) designs are composed of different blocks running multiple applications with varying power requirements.

Power format standards, like Common Power Format (CPF) and the Unified Power Format (UPF), are evolving to establish a power definition that can be used throughout the design, verification, and implementation stages. While development of a consistent power definition seems promising, it has direct implications on the complex verification issues that engineers face in debugging power‐aware designs and the types of solutions needed to address them.
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