All Categories : Technical Papers Bookmark and Share

Title : Introducing Functional Qualification
Company : SpringSoft, Inc.
File Name : Functional_Qualification_Whitepaper.pdf
Size : 230669
Type : application/pdf
Date : 11-Mar-2010
Downloads : 25

Rate This File
5 Stars
4 Stars
3 Stars
2 Stars
1 Star

Functional verification consumes a significant portion of the time and resources devoted to the typical design project. As chips continue to grow in size and complexity, designers must increasingly rely on a dedicated verification team to ensure that systems fully meet their specifications.

Verification engineers have at their disposal a set of dedicated tools and methodologies for verification automation and quality improvement. In spite of this, functional logic errors remain a significant cause of project delays and re‐spins. A key reason is that two important aspects of verification environment quality – the ability to propagate the effect of a bug to an observable point and the ability to observe the faulty effect and thus detect the bug – cannot be analyzed or measured. Existing methods, such as functional coverage and code coverage, largely ignore these two aspects, allowing functional errors to escape the verification process despite excellent coverage scores. Existing tools are simply unable to assess the overall quality of simulation‐based functional verification environments.

The Certitude Functional Qualification System from SpringSoft incorporates unique technology that measures and drives improvement of all aspects of functional verification quality for simulation‐based environments. This paper describes the fundamental aspects of functional verification that remain invisible to existing verification tools. It then introduces the origins and main concepts of a technology that allows this gap to be closed: Mutation‐based testing. It describes how SpringSoft uses this technology to deliver Certitude, the industry’s first functional qualification solution. Finally, it describes how
User Reviews More Reviews Review This File
Downstream : Solutuions for Post processing PCB Designs

Aldec

Featured Video
Jobs
R&D Hardware Electrical Engineering Associate for Applied Research Laboratories UTA at Austin, Texas
IC Design Verification Engineer for Coherent Logix at Austin, Texas
Digital Design Engineer for Cirrus Logic, Inc. at Austin, Texas
Upcoming Events
Design and Verification Conference and Exhibition (DVCon) at DoubleTree by Hilton San Jose 2050 Gateway Place San Jose CA - Feb 25 - 28, 2019
Geodesign Summit 2019 at Redlands CA - Feb 25 - 28, 2019
Mobile World Congress 2019 at Fira Gran Barcelona Spain - Feb 25 - 28, 2019
WTS 2019 at London United Kingdom - Mar 12 - 13, 2019
DownStream: Solutions for Post Processing PCB Designs
TrueCircuits: IoTPLL



Internet Business Systems © 2019 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise