Mentor Graphics and TSMC Address Advanced Node Fill Requirements Using Calibre SmartFill

WILSONVILLE, Ore. — (BUSINESS WIRE) — September 14, 2011 — Mentor Graphics Corporation (NASDAQ: MENT) today announced a collaboration with TSMC to support SmartFill functionality in the Calibre® YieldEnhancer product for TSMC’s manufacturing processes starting at 65nm. The analysis and automatic filling capabilities of the SmartFill solution allow designers to achieve IC fill constraints with minimal impact on circuit performance in a single pass without manual customization or modification.

“We have worked closely with Mentor to create an effective fill solution for advanced nodes. SmartFill is designed to handle the new fill requirements of our most advanced process technologies,” said Suk Lee, director of Design Infrastructure Marketing at TSMC. “Our collaboration with Mentor cell-based fill is particularly important because it makes writing advanced node fill decks easier, while reducing runtime and output file size by placing cells rather than individual polygons on multiple layers.”

New Capabilities for Advanced Fill Requirements

SmartFill integrates the full range of the Calibre analysis engines into the fill process to achieve fully optimized fill without manual iterations. It provides advanced capabilities such as multi-layer fill shapes and the ability to add fill cells, which are automatically inserted into a layout based on analysis of the design.

SmartFill uses continuous, multi-dimensional functions in place of linear pass-fail conditions, enabling finer resolution of complex fill algorithms that cannot be performed with single-dimensional design rules alone. This allows customers to optimize for multiple factors such as density and perimeter.

Since SmartFill employs standard Calibre interfaces, it fits seamlessly into the customer’s existing design environment. It supports timing-aware fill with back annotation of fill shapes into all industry-leading design databases to enable final timing verification. It also allows customers to provide a list of critical nets that receive special treatment during the fill procedure.

“The sophistication of filling strategies has increased dramatically over the last couple of nodes due to the increasing complexity in both manufacturing and design aspects impacted by fill,” said Joseph Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “SmartFill provides designers with a solution that allows them to generate fill that has been optimized to their specific design and cycle time needs, while still achieving TSMC’s advanced fill requirements.”

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues over the last 12 months of about $915 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com/.

(Mentor Graphics and Calibre are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)



Contact:

Mentor Graphics
Gene Forte, 503-685-1193
Email Contact
or
Sonia Harrison, 503-685-1165
Email Contact




Review Article Be the first to review this article

 Advanced Asembly

Featured Video
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
You’re Invited! SEMI’s Innovation for a Transforming World
intelThe Dominion of Design
by intel
The Long Game: Product and Security Assurance
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Setting a High Standard for Standards-Based IP
Jobs
Senior HID Sensor Algorithm Architect for Apple Inc at Cupertino, California
Staff SerDes Applications Design Engineer for Xilinx at San Jose, California
Senior Staff Field Application Engineer for Global Foundaries at Santa Clara, California
Test and Measurement System Architect for Xilinx at San Jose, California
NAND Hardware Engineer for Apple Inc at Cupertino, California
Pre-silicon Design Verification Engineer for Intel at Santa Clara, California
Upcoming Events
Innovation for a Transforming World -virtual Event at United States - Jul 13 - 14, 2021
DesignCon 2021 at San Jose McEnery Convention Center San Jose, CA San Jose CA - Aug 16 - 18, 2021
SEMICON Southeast Asia 2021 Hybrid Event at Setia SPICE Convention Centre Penang Malaysia - Aug 23 - 27, 2021
7th International Conference on Sensors & Electronic Instrumentation Advances (SEIA' 2021) at Palma de Mallorca, Mallorca balearic islands) Spain - Sep 14 - 16, 2021
Verific: SystemVerilog & VHDL Parsers



© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise