Mentor Graphics Adds User Defined Fault Models and Cell-Aware ATPG to Improve IC Test Quality

ANAHEIM, Calif. — (BUSINESS WIRE) — September 19, 2011Mentor Graphics Corporation (NASDAQ: MENT) today announced new capabilities in the Tessent® TestKompress® and the Tessent FastScan™ tools that enable higher defect coverage and lower defect per million (DPM) levels for quality-critical applications like military, medical, automotive, and many others. User defined fault models (UDFM) and a new cell-aware ATPG flow together allow customers to target subtle shorts and open defects internal to standard cells that are not adequately detected with the standard stuck-at or transition fault models.

“Cell-aware testing based on UDFM allows us to increase the quality of our manufacturing test by catching defects that would have gone undetected using conventional fault models,” said Jeff Rearick, senior fellow at AMD. “Traditional fault models ensure that the periphery of standard cells and the interconnections between them are fully tested, but can miss some bridging or open defects internal to the cells. With the UDFM and cell-aware capabilities, TestKompress can generate patterns to specifically target these additional defects, giving us higher confidence in our production testing with minimal impact to test time. This takes us a big step closer to true zero defect quality control.”

Cell-aware fault models are generated using a one-time cell library characterization flow, which uses the Calibre® extraction tools and the Mentor® Eldo® product for transistor level fault simulation. Once characterization has been performed, the cell internal fault models are automatically incorporated into TestKompress pattern generation using the new UDFM syntax. Cell library characterization is also available as a service from Mentor Consulting. Additionally, customers can use the UDFM capability to define any proprietary fault model that may be needed to improve quality levels for their specific process or application.

“As we move to more advanced process nodes, we see a variety of new failure modes that must be addressed by IC testing,” said Steve Pateras, product marketing director at Mentor Graphics. “UDFM allows customers to adapt to these new faults without waiting for commercial fault model libraries to catch up. Mentor continues to push the envelope on automated IC testing with new technology to maintain the highest test quality while reducing test development effort and, more importantly, the production cost of testing.”

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues over the last 12 months of about $915 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site:

(Mentor Graphics, Mentor, Tessent, Eldo, TestKompress and Calibre are registered trademarks and FastScan is a trademark of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)


Mentor Graphics
Gene Forte, 503-685-1193
Email Contact
Mentor Graphics
Sonia Harrison, 503-685-1165
Email Contact

Review Article Be the first to review this article
DAC 2020

 True Circuits: Ultra PLL

Featured Video
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Meet the New Cylynt, Fighting Software Piracy Around the Globe
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Smart Assembly of SoC Designs
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Senior Layout Engineer for EDA Careers at EAST COAST, California
Software Engineer for EDA Careers at RTP, North Carolina
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Upcoming Events
57th Design Automation Conference 2020 at San Francisco CA - Jul 19 - 23, 2020
SEMICON West 2020 - Virtual Event at - Jul 20 - 23, 2020
Semicon Southeast Asia 2020 at MITEC Kuala Lumpur Malaysia - Aug 11 - 13, 2020
Drive World Conference & Expo at Santa Clara Convention Center Santa Clara CA - Aug 11 - 13, 2020
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers

© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise