X-FAB Qualifies Cadence Physical Verification System for All Process Nodes

SAN JOSE, CA -- (MARKET WIRE) -- Oct 05, 2011 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that X-FAB, a leading foundry group for analog/mixed-signal semiconductor applications, has qualified the Cadence® Physical Verification System for the majority of its process technologies. Foundry qualification means that X-FAB has given its stamp of approval for silicon accuracy of the Cadence Physical Verification System across all of its process nodes, and that mixed-signal customers can reap new performance and productivity advantages enabled by its tight integration into the Cadence Virtuoso® and Encounter® flows.

"Creating an advanced mixed-signal SoC presents significant challenges," said Dr. Jens Kosch, chief technology officer at X-FAB. "Our customers welcome any opportunity to streamline the development process, so we were pleased to qualify and endorse the Cadence Physical Verification System for our process technologies at X-FAB."

The Cadence Physical Verification System delivers in-design and final signoff design rule checking (DRC) and layout versus schematic (LVS) verification at transistor, cell, block, and full-chip/SoC levels. It integrates with industry-standard end-to-end digital and custom/analog flows, enabling more efficient Silicon Realization methodologies.

"Design teams prefer to stay within the same environment for design, implementation, and verification to shorten turnaround time and ensure design quality. This qualification means X-FAB customers can confidently conduct all required physical verification using the Cadence Physical Verification System, remaining in the design and implementation cockpit to improve productivity," said John Murphy, group director, alliances marketing at Cadence. "We worked closely with X-FAB to address all its stringent verification qualification requirements, meeting and exceeding all signoff parameters. This type of deep collaboration with leading foundries is an essential element of the EDA360 vision."

By tightly integrating design rule checking into the Cadence implementation technologies, design teams will be able to validate against signoff DRC validation as they edit, allowing them to find and fix errors earlier in their flow while saving them time in longer loops through standalone signoff solutions. The result is faster time to tapeout. Cadence and X-FAB continue to work closely together to provide validated signoff verification decks for their mixed-signal customers.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, Virtuoso, Encounter and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

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For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226

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