Mentor Graphics Delivers First ARM Cortex and AMBA Family Verification Solution that Spans Simulation and Emulation

WILSONVILLE, Ore. — (BUSINESS WIRE) — November 10, 2011Mentor Graphics Corporation (NASDAQ: MENT) today announced that its industry-leading Questa® and Veloce® functional verification platforms have expanded their support for designs based on the latest ARM Cortex processors and AMBA bus interfaces. This enables both hardware and software engineers to fully verify their multi-core ARM-based designs seamlessly across the Questa verification and Veloce emulation platforms.

The Mentor® library of accelerated Instruction Set Simulation (ISS) models that currently includes all ARM Cortex A-family, Cortex R-family, and Cortex M-family processors, has added support for ARM's newest Cortex A7 MPCore™ and Cortex A15 MPCore products. Multi-core SoC designs incorporating these processors can now be verified across both the Questa and Veloce verification platforms with the Questa Codelink® product’s unique ‘DVR-style’ of simulation/emulation playback for debugging. Engineers can combine their RTL processor models with the ISS processor models, which can be hot-swapped on-the-fly during simulation. This enables engineers to realize the benefits of accelerated simulation, without sacrificing accuracy for debugging. By making these models portable to the Veloce emulation platform, software and hardware can be verified at even higher speeds, all while enabling off-line debugging, leaving high-in-demand emulators to run even more regression tests.

Mentor has also expanded its library of verification IP (VIP) with the addition of AMBA® 4 ACE support to Questa Verification IP. Building on the previously announced support for protocols such as AMBA, DDR, Ethernet and PCI Express, Mentor continues to maintain a comprehensive VIP solution across both simulation and emulation for ARM-based SoCs.

The ACE protocol adds hardware support for cache coherency, bringing benefits in both power and performance, but presenting some unique and complex challenges to verification engineers. Mentor has leveraged industry expertise in verification methodology, including OVM and UVM, AMBA and cache-coherent, multi-processor system verification to deliver the industry’s most comprehensive verification solution for ACE. Engineers can now completely verify and integrate IP supporting ACE quickly and with reduced cost with the comprehensive test, coverage, check and debug capabilities built into the Questa VIP.

“We have worked directly with ARM and mutual customers to put in place verification solutions that enable designers to design and verify next-generation SoCs that leverage ARM’s big.LITTLE processing,” said John Lenyo, general manager of the Design Verification Technology division of Mentor Graphics. “Our unique Questa and Veloce functional verification platforms, optimized to support multi-core hardware and software verification, enable a new class of SoC-Level Verification that allows our users to deliver on their first-to-market plans.”


The Questa Codelink support for ARM Cortex A7, Cortex A15, other Cortex A-family, Cortex R-family, and Cortex M-family processors and Questa Verification IP support for AMBA4 ACE is available immediately.

About Mentor Graphics

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues over the last 12 months of about $915 million. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon, 97070-7777. World Wide Web site:

(Mentor, Questa, Veloce and CodeLink are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)


Mentor Graphics
Carole Dunn, 503-685-4716
Email Contact
Ry Schwark, 503-685-1660
Email Contact

Review Article Be the first to review this article

 True Circuits: Ultra PLL

Featured Video
Latest Blog Posts
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Smart Assembly of SoC Designs
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
D2S Brings GPU Acceleration to Semiconductor Design and Manufacturing
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Software Engineer for EDA Careers at RTP, North Carolina
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Senior Layout Engineer for EDA Careers at EAST COAST, California
Upcoming Events
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020 at Limassol Hotel, Amathus Area, Pareklisia Cyprus - Jul 6 - 8, 2020
57th Design Automation Conference 2020 at San Francisco CA - Jul 19 - 23, 2020
SEMICON West 2020 - Virtual Event at - Jul 20 - 23, 2020
Semicon Southeast Asia 2020 at MITEC Kuala Lumpur Malaysia - Aug 11 - 13, 2020

© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise