Atrenta Will Discuss SoC Realization at VLSI India Conference 2012

Company Participates in Panel Discussion entitled “SoC Realization – A Bridge to New Horizons or a Bridge to Nowhere?”  

NEW DELHI , India -- January 3, 2012

What:

Mr. Sathyam Pattanam, Senior Director Engineering for GenSys™ and SpyGlass® Low Power Verification Products at Atrenta, will participate in a panel entitled “SoC Realization – A Bridge to New Horizons or a Bridge to Nowhere?” at the VLSI Design Conference 2012. 

System on Chip (SoC) Realization is the emerging market that bridges the gap between an electronic system concept and its implementation in silicon.

In the panel, Mr. Pattanam will discuss the merits of early analysis methodologies and solutions, together with panelists from other semiconductor and EDA companies including:

  • Broadcom - Subhash Chintamaneni, Senior Manager, DTV Division
  • Cadence – Raju Pudota, Group Director, Flash IP Engineering
  • Freescale – Ganesh Guruswamy, Vice President and Country Manager
  • InfoTech Enterprises – Ram Gollapudi, General Manager, Hi-tech Business Unit
  • Seer Akademi – Srikanth Jadcherla, Chairman and CEO, Electronics Education Company
  • ST – Rajamohan Varambally, Director Technology R&D
  • Synopsys – Vikas Gautam, Director, Verification and IP products
  • TI –Mahesh Mehendale, TI Fellow and Director, Center of Excellence for VLSI Architectures

Professor P.P. Chakrabarti, IIT Kharagpur, will moderate the panel to explore and discuss the meaning of SoC Realization and its impact on the cost and schedule for advanced SoC designs.

When:

January 9, 2012 from 5:25pm to 6:40pm IST


Where:

VLSID 2012, HICC, Hyderabad, India

Why:

SoC design promises to revolutionize a vast array of products and markets, but the cost of design for SoC devices is growing at a rapid pace. Shrinking market windows necessitate reuse of semiconductor IP, either from third-party sources or prior internal designs. But the quality and completeness of this IP is often not completely known. Structured design methodologies that focus on early identification and correction of design issues, rigorous methods to qualify semiconductor IP and automated approaches to assembling the components of an SoC promise to address many of the cost and schedule challenges.

Notes:  

 

For more information, contact:

Atrenta

Charu Puri

Tel: +91-9810313320

Email: cpuri@atrenta.com

PR Agency:

Lee PR

Liz Massingill  (liz@leepr.com)

Tel: +1-650-363-0142

– end –

Atrenta, SpyGlass, GenSys and the Atrenta logo are registered trademarks of Atrenta Inc. All others are the property of their respective holders.





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