Apache Design April 2012: RTL Power Model (RPM) Wins DesignVision Award

RTL Power Model (RPM) Wins DesignVision Award

Apache's RTL Power Model (RPM™) recently won the DesignCon 2012 DesignVision Award for the System Modeling and Simulation Tools category.

Apache earned this prestigious award for innovative electronics tools that simplify customer design processes.

Launched in late 2011, RPM technology enables organizations to optimize a wide range of power-sensitive applications, such as ultra-low-power electronics. RPM helps ensure that power-related decisions can be made with confidence early in the design flow by bridging the power gap from register-transfer-language (RTL) design to physical implementation.

This is the second DesignVision Award for Apache; the first was for PowerArtist™ in 2009.

Press Release

Power Issues for Chip and Board Webcast

This EDN hosted webcast was held in January and was sponsored by ANSYS and Tektronix. Presenters were Arvind Shanmugavel, Apache Design, and Randy White, Tektronix.

Power used to be a secondary concern when it comes to chip or system design, but with the rapid rise in importance of mobile devices, increasing chip densities, and a rise in the levels of concurrency, power consumption, power dissipation, heat dissipation, and power integrity are becoming major primary design considerations at all stages in the design flow. Many chip design techniques are making this problem more difficult, such as multiple power domains and clock-gating, while high-speed interfaces are creating problems with board layouts and 3D packaging techniques are raising many kinds of new challenges. Power management is an important topic for every design company to remain competitive, to increase yields, and to deal with the longevity issues required for emerging industries such as automotive.

If you missed the live webcast, you can register and view the arhcived presentation. Click here.

ANSYS and Apache - The SMART Solution

Advancing low-power innovation through simulation-driven product development.

Take a minute to view this short informative video.

Apache Community

Upcoming Events

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Download the paper presented at ISQED: Chip-Package Co-design Time and Frequency Domain Analysis

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WebEx Webinar
April 30, 2012

TSMC Technology Symposium
San Jose, CA
April 17, 2012

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Tel Aviv, Israel
May 1 - 2, 2012

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San Francisco, CA
June 4 - 6, 2012

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In the News

Popular White Papers

  • NEW - Electronic Power and Thermal Management
  • RTL Design-for-Power (DFP) Methodology
  • Low Power Design Analysis
  • Power and Noise Integrity for Analog/Mixed-Signal Designs
  • PathFinder™: Solution for Full-chip IC ESD Integrity
  • Advanced Modeling for Chip, Package, System Co-analysis/Co-optimization
  • Power and Signal Line EM Design and Reliability Validation Challenges
  • Technologies for Power, Signal, Thermal, and EMI Sign-off

To download these White Papers from our website, click here . Valid account required.

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