Apache Customers Present at DAC 2012, Booth #1813

 

49th Design Automation Conference
San Francisco Moscone Center
June 4 - 6, 2012

Apache Customers Share Low Power Design Experiences

Designers from leading semiconductor companies including AMD, Aptina, Cienna, LSI, Nvidia, NXP, Renesas, Samsung, and ST will be speaking about best practices and experiences on power, reliability, Chip-Package-System and 3D-IC.

For more information and registration, click here.

Low-Power Designs

  • Enabling Accurate and Efficient RTL Power Analysis and Optimization Methodology for Low Power Designs - Renesas
  • Power Noise and Other Simulation Considerations for Energy-efficient SoCs - LSI

Power Delivery Integrity

  • A Chip-Package Simulation Methodology for Ultra-Large Low-Power Mobile ICs - Samsung-SSI
  • Power Noise Analysis with Silicon Correlation Results for Complex 32nm ASIC Designs - Ciena

Analog / Mixed-Signal Designs

  • Full-chip Substrate Noise Coupling Analysis and Noise Isolation Structure Design Experiments - NXP Semiconductor
  • Evaluating Design Options and Trade-offs through Full-chip Substrate and Metal Layer Noise Analysis for a Commercial Image Sensor Chip - Aptina

Advanced Reliability Challenges

  • Electrostatic Discharge (ESD) Simulation and Sign-off Considerations for Complex GPU and APU Designs - AMD
  • A Dynamic Simulation Methodology for Diagnosis and Predictive Simulation of HBM/CDM Events - nVidia

Chip-Package-System

  • Simultaneous SI and PI Analysis for High-speed IO Designs for Mobile Applications - ST-Ericsson
  • System-level Power Noise Analysis and Optimization with Measurement Correlation Results for Multiple DRAMs with TSV - Samsung-DRAM

3D-IC Designs

  • Considerations for Designing and Simulating Memory Interfaces for 3D/Stacked-die Designs - UCSD

Apache Power Methodology

Apache's Power Team Experts will be presenting our industry leading power analysis and optimization solutions for power budgeting, power delivery, reliability, Chip-Package-System and 3D-IC.

For more information and registration, click here.

  • Ultra-Low-Power Methodology Design Simulation: An RTL-to-Gate Approach
  • Reliability Analysis for 28/20nm Electromigration (EM) and Electrostatic Discharge (ESD)
  • Achieving Low Power Design Closure with Chip-Package-System Design Approach
  • RedHawk-3DX: The Fourth Generation RedHawk for 20nm and Stacked-die Designs

 

 

Apache Activities @ DAC

 

 

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© 2012 Apache Design, Inc. All rights reserved.

 




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