Tanner EDA at DAC 2012: New Products and Solutions for Analog Designers, Mixed-signal Designers, and MEMS Designers

MONROVIA, California – May 30, 2012 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs) and MEMS devices, has announced two new products for DAC 2012 and will be offering a series of demonstrations for analog, mixed-signal and MEMS designers.

The new Tanner Analog FastSPICE  solution, an add-on to Tanner EDA’s front end and full flow analog/mixed-signal design suites, brings Berkeley Design Automations Analog FastSPICE platform to Tanner EDA customers, delivering foundry-certified nanometer SPICE accuracy at speeds 5x-10x faster than any other simulator on a single core and an additional 2x-4x performance uptick with multithreading. The HiPer Simulation A/MS solution, which offers T-Spice analog design capture and simulation together with Aldec’s Riviera-PRO™ mixed language digital simulator, allows both analog and digital designers to seamlessly resolve A/MS verification problems from one cohesive, integrated platform.

Live demonstrations and presentations at the Tanner EDA booth will include:

HiPer Silicon Product Demo: Full-flow analog design suite - now including Open Access! (30 Mins)
HiPer Simulation AFS Demo: The latest front-end offering, from Tanner EDA and Berkeley Design Automation (30 Mins)
HiPer DevGen: An add-on tool that breaks through the analog design layout bottleneck, automatically generating differential pairs, current mirrors, resistor dividers and MOSFETs (30 Mins)

HiPer Simulation AMS Demo: Tanner’s latest analog/mixed-signal offering that bridges analog and digital verification by integrating T-SPICE with Aldec’s Riviera-PRO (30 Mins)
HiPer Silicon AMS Demo: A cohesive analog/mixed-signal flow that bridges analog and digital verification and adds synthesis, static timing and place & route (40 Mins)


L-Edit MEMS Designer Demo: Demonstrating how L-Edit combines with high-performance add-ins that include curve tools, DXF import/export and design rule checking (DRC) (30 Mins)
MEMS 3D Solid Modeler Demo: The latest offering from Tanner EDA & SoftMEMS that creates a 3D view of a MEMS device from a selected layout area and fabrication process description (30 Mins)


PDKs: An essential element of analog design success (30 Mins)

Tanner EDA will be in Booth # 1126 at DAC 2012 in the Moscone Center in San Francisco, California, from June 4th to 6th.   Click here to reserve meeting or demonstration time.

About Tanner EDA

Tanner EDA provides a complete line of software solutions that drive innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and MEMS. Customers are creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity and enable a low total cost of ownership (TCO). Capability and performance are matched by low support requirements and high support capability as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.

Founded in 1988, Tanner EDA solutions deliver just the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.

HiPer Verify and HiPer Silicon are trademarks of Tanner Research, Inc. Analog FastSPICE, AFS Nano, and WaveCrave are trademarks of Berkeley Design Automation, Inc. Berkeley Design and BDA are registered trademarks of Berkeley Design Automation, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.

#          #          #

Review Article Be the first to review this article

Featured Video
Roberto FrazzoliEDACafe Editorial
by Roberto Frazzoli
IBM’s 2nm chip; EDA updates; AI updates; acquisitions
More Editorial  
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Next Week’s Main Event: The ESD Alliance CEO Outlook
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
Automating the UVM Register Abstraction Layer (RAL)
Staff SerDes Applications Design Engineer for Xilinx at San Jose, California
Sr Engineer - RF/mmWave IC Design for Global Foundaries at Santa Clara, California
Test and Measurement System Architect for Xilinx at San Jose, California
Pre-silicon Design Verification Engineer for Intel at Santa Clara, California
SerDes Applications Design Engineer for Xilinx at San Jose, California
ASIC SoC Verification Engineer for Ericsson at Austin, Texas
Upcoming Events
DVCon China 2021 at Shanghai China - May 26, 2021
CadenceLIVE Americas 2021 at United States - Jun 8 - 9, 2021
DesignCon 2021 at San Jose McEnery Convention Center San Jose, CA San Jose CA - Aug 16 - 18, 2021
SEMICON Southeast Asia 2021 Hybrid Event at Setia SPICE Convention Centre Penang Malaysia - Aug 23 - 27, 2021
Verific: SystemVerilog & VHDL Parsers

© 2021 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise