Cadence Collaborates on 3D-IC Design Infrastructure With TSMC

SAN FRANCISCO, CA -- (Marketwire) -- Jun 04, 2012 -- DAC Booth # 1930 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced its collaboration with TSMC on 3D-IC design infrastructure development.

3D-ICs require co-design, analysis and verification of heterogeneous chips and silicon carriers. Coming from multiple disciplines and product areas, TSMC and Cadence teams worked together to create and integrate features to support this new type of design, culminating in the test-chip tapeout of TSMC's first heterogeneous CoWoS (Chip-on-Wafer-on-Substrate) vehicle.

Cadence 3D-IC technology enables multi-chip co-design between digital, custom and package environments incorporating through-silicon vias (TSVs) on both chips and silicon carriers, and supports micro-bump alignment, placement, routing and design for test. It includes key 3D-IC design IP, such as a Wide IO controller and PHY to support Wide IO memories. Test modules were created using the Cadence Encounter RTL-to-GDSII flow, Virtuoso custom/analog flow, and Allegro system-in-package solutions.

"In 2012 3D-IC became a viable option for real-world chip design," said John Murphy, group director, Strategic Alliances at Cadence. "For 10 years, Cadence has invested in SiP (System in Package) and 3D-IC design capabilities. Now we can share this knowledge with designers to bring this versatile technology to market."

Cadence 3D-IC technology helps enable device designs that will be incorporated into TSMC's recently introduced CoWoS process. CoWoS is an integrated process technology that bonds multiple chips in a single device to reduce power, improve system performance and reduce form factor.

"Big leaps in electronic design don't happen without strong collaboration, and our partnership with Cadence in CoWoS design is a good example," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "For 3D-IC design ecosystem readiness, Cadence played an important role in the development of design technology and the necessary IP."

Learn about 3D-IC Technology at DAC 2012 in San Francisco
Cadence and TSMC will offer a joint tutorial on Monday, June 4 at DAC describing the practical approaches to 3D-IC, TSV and Wide IO. The companies will share the experiences gained in the design, manufacturing, test and assembly of 3D-IC CoWoS chips.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

Cadence, Virtuoso, Encounter and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners.

Add to Digg Bookmark with del.icio.us Add to Newsvine

For more information, please contact:
Dean Solov
Cadence Design Systems, Inc.
408-944-7226

Email Contact 





Review Article Be the first to review this article
Aldec

 True Circuits: Ultra PLL

Featured Video
Latest Blog Posts
Bob Smith, Executive DirectorBridging the Frontier
by Bob Smith, Executive Director
Virtual 2020 CEO Outlook Set for June 17
Colin WallsEmbedded Software
by Colin Walls
Multiple constructors in C++
Jobs
Senior Analog Design Engineers #5337 for EDA Careers at EAST COAST, California
Senior Layout Engineer for EDA Careers at EAST COAST, California
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
Software Engineer for EDA Careers at RTP, North Carolina
Upcoming Events
Sensors Expo & Conference at McEnery Convention Center 150 W. San Carlos Street SAN JOSE CA - Jun 22 - 24, 2020
Nanotech 2020 Conference and Expo at National Harbor MD - Jun 29 - 1, 2020
IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020 at Limassol Hotel, Amathus Area, Pareklisia Cyprus - Jul 6 - 8, 2020
57th Design Automation Conference 2020 at San Francisco CA - Jul 19 - 23, 2020



© 2020 Internet Business Systems, Inc.
25 North 14th Steet, Suite 710, San Jose, CA 95112
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise