Xilinx Targets Reduced OpEx and CapEx for Network Operators with Expanded FEC IP Core Offering

Comprehensive Offering of Forward Error Correction IP Cores Announced at WDM & Next Generation Optical Networking Conference

SAN JOSE, Calif., June 18, 2012 — (PRNewswire) — Xilinx, Inc. (NASDAQ: XLNX) today announced its expanded Forward Error Correction (FEC) Intellectual Property (IP) Core offering at the WDM and Next Generation Optical Networking 2012 Conference being held in the Grimaldi Forum, Monaco. The offering includes GFEC, EFEC and high gain FEC (xFEC) solutions used to obtain error control in signal transmission and extend the distance of a transmission that reduces the number of regenerators (hops) along the route, which reduces OpEx and CapEx costs for network operators.

Xilinx designed these FEC IP cores with a common interface to accelerate product development, minimize system level integration time, maximize design reuse and reduce time-to-market. The ultra compact, high-performance FEC cores – which include GFEC IP cores for 2.5G, 10G, 40G, 100G applications, legacy 10G EFECs and a Xilinx Extended FEC (xFEC) IP core for 100G applications – were optimized specifically for Xilinx FPGAs to occupy less silicon real estate than non-Xilinx IP cores, making them the smallest FEC cores available. Xilinx is also working to add 400G GFEC for leading edge applications to be available Q2 2013. Combined with partial reconfiguration, these IP cores optimized for Xilinx FPGAs enable customers to integrate multiple FEC standards on multiple interfaces, while reducing product costs, power consumption and maximize network interoperability.

"As bandwidth demands increase and the tolerance for errors and latency decreases, system designers are looking for new ways to expand available bandwidth and improve the quality of transmission," said Nick Possley, Xilinx senior director of wired communications. "To solve these challenges, Xilinx has extended our leadership position in the OTN marketplace by delivering this expanded offering of FEC IP cores for 2.5G, 10G, 40G, 100G and 400G applications. The power/performance available in our 7 series FPGA family combined with this FEC portfolio enables our customers to achieve higher data rates, increase bandwidth and reduce system costs within the OTN application space."

The use of forward error correction maintains error control between the source (transmitter) sending redundant data signals and the destination (receiver) that recognizes only the portion of the data containing no apparent errors. Used in all OTN systems, FEC provides coding gain that allows users to transmit a signal over a greater distance by correcting errors that can happen as the signal-to-noise ratio decreases with distance, yet still achieve the same error rate at the far end receiver.

Different FEC schemes provide different levels of coding gain. The higher the coding gain, the greater the distance an optical signal can be transmitted. As an example, the Xilinx 100G Extended FEC (xFEC) provides an industry leading 9.4dB NECG at 6.7 percent OH that increases 100G transmission distances and reduces 100G transmission power.

The coding gain provided by FEC is used to do multiple functions including increasing the maximum span length and/or the number of spans that results in extending system reach. This is also useful for increasing the number of dense wavelength division multiplexing (DWDM) channels in a system which is typically limited by the output power of the amplifiers being used. This coding gain also decreases the power per channel and increases the number of channels or relaxes the component parameters (e.g. launched power, eye mask, extinction ratio, noise figures, filter isolation) for a given link and lowers the component costs.

Availability and Ordering Information
The Xilinx OTU1, 2, 3 and 4 (2.5G, 10G, 40G and 100G) GFEC IP cores are compliant to the ITU G.709 standard and are available today. The 100G high gain xFEC will be available in December 2012. Xilinx will also be adding other EFEC standard implementations based on customer demand.

Xilinx FEC IP cores are cost competitive and only require a single project license with no recurring royalty fee. For full access to all core functionality in simulation and in hardware, a license for a core must be purchased. Visit the Optical Transport Network Solutions page to order the license. Contact your local Xilinx sales representative or FAE for pricing and availability of Xilinx FEC IP cores.

About Xilinx
Xilinx is the world's leading provider of All Programmable technologies and devices, going beyond traditional programmable logic to enable both hardware and software programmability, integrate both digital and analog mixed-signal functions, and allow new levels of programmable interconnect in both monolithic and multi-die 3D ICs. The company's products are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. For more information, visit www.xilinx.com.


Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Bruce Fienberg
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SOURCE Xilinx, Inc.

Xilinx, Inc.
Web: http://www.xilinx.com

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