Microsemi Broadens Communications Timing Portfolio with Family of Buffers

New Solutions Support Industry's Lowest Additive Jitter Combined with Best Power Supply Noise Rejection Performance

ALISO VIEJO, Calif., Dec. 5, 2012 — (PRNewswire) — Microsemi Corporation (Nasdaq: MSCC), a leading provider of semiconductor solutions differentiated by power, security, reliability and performance, today expanded its communications timing portfolio with its first family of clock distribution differential fan-out buffers. The 28-part family of buffers supports clock rates of up to 750 megahertz (MHz); two types of outputs, low voltage positive emitter coupled logic (LVPECL) and low voltage differential signaling (LVDS); and multiple fan-out ratios. Internal and external terminations for inputs eliminate the need for external peripheral components. In addition, the ultra-low additive output jitter leaves the majority of the jitter budget to the high speed transceivers. The combination of these features results in lower bill-of-material (BOM) costs.

The new clock buffers devices are synergistic with Microsemi's broad timing portfolio and, when used together, provide customers improved board performance and complete timing solutions.

"Broadening our current timing and synchronization offering with our new buffer family allows us to offer customers a complementary building block for clock generation and synthesis products," said Maamoun Seido, vice president and business unit manager of Microsemi's timing products. "Communications is a key area of focus for Microsemi. With our investments in this area, including the acquisition of Maxim's timing, synthesis and synchronization business earlier this year, we now have the roadmaps and resources in place to capitalize on growing opportunities in this market segment."

About Microsemi's New Buffer Family

Microsemi's high-performance buffers deliver the industry's lowest additive jitter combined with best power supply noise rejection performance. This preserves signal integrity by adding ultra-low jitter and filtering noise from power supplies, resulting in better performance while simplifying engineering board design efforts. In addition, the flexible I/O structure and internal on chip input terminations eliminate the need for external components, which reduces BOM costs. Microsemi's new buffer family includes:

LVPECL Output Solutions:

Input Termination

1:2 Fan-out

QFN-16

3x3 mm

1:4 Fan-out

QFN-16

3x3 mm

1:6 Fan-out

QFN-32

5x5 mm

1:8 Fan-out

QFN-32

5x5 mm

2:6 Fan-out

QFN-32

5x5 mm

2:8 Fan-out

QFN-32

5x5 mm

External

P/N  ZL40200

P/N ZL40202

P/N  ZL40204

P/N  ZL40206

P/N  ZL40208

P/N  ZL40210

P/N  ZL40224

Internal

P/N  ZL40201

P/N  ZL40203

P/N  ZL40205

P/N  ZL40207

P/N  ZL40209

P/N  ZL40211

P/N  ZL40225

LVDS Output Solutions:

Input Termination

1:2 Fan-out

QFN-16

3x3 mm

1:4 Fan-out

QFN-16

3x3 mm

1:6 Fan-out

QFN-32

5x5 mm

1:8 Fan-out

QFN-32

5x5 mm

2:6 Fan-out

QFN-32

5x5 mm

2:8 Fan-out

QFN-32

5x5 mm

External

P/N  ZL40212

P/N ZL40214

P/N  ZL40216

P/N  ZL40218

P/N  ZL40220

P/N  ZL40222

P/N  ZL40226

Internal

P/N  ZL40213

P/N  ZL40215

P/N  ZL40217

P/N  ZL40219

P/N  ZL40221

P/N  ZL40223

P/N  ZL40227


1 | 2  Next Page »



Review Article Be the first to review this article
Aldec

New Customer Special

Featured Video
Editorial
Roberto FrazzoliEDACafe Editorial
by Roberto Frazzoli
Linley Fall Processor Conference 2020 – Part One
More Editorial  
Latest Blog Posts
Anupam BakshiAgnisys Automation Review
by Anupam Bakshi
A Unified Flow for Embedded Systems Development
Colin WallsEmbedded Software
by Colin Walls
Time for a new programming paradigm?
Jobs
Director Technical and Corporate Marketing for EDA Careers at San Jose, California
Test Engineer for Marvell Semiconductor at Santa Clara, California
Product Line Manager for EDA Careers at Multiple, North Carolina
Principle Digital Design ASIC Manager for EDA Careers at RTP, North Carolina
Senior Application Engineer Formal Verification for EDA Careers at San Jose and Austin, California
IC Design Engineer - SoC Integration for Xilinx at San Jose, California
Upcoming Events
International Conference on Computer Aided Design (ICCAD) 2020 at San Diego Mission Bay Resort San Diego CA - Nov 2 - 5, 2020
2020 International Conference On Computer Aided Design at San Diego Mission Bay Resort San Diego CA - Nov 2 - 5, 2020
SUBMIT YOUR PAPER TO THE 2020 ITC! at Washington DC - Nov 3 - 5, 2020
TrueCircuits:



© 2020 Internet Business Systems, Inc.
670 Aberdeen Way, Milpitas, CA 95035
+1 (408) 882-6554 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy PolicyAdvertise