Design Solution for Embedded PowerMOS Transistor Arrays
May 15, 2013 -- Grenoble, France -- Backend verification specialist EdXact SA today announces the availability of a new design aid for designers of PowerMOS transistor arrays. The new option comes along with Viso™, now available in version 1.6.
The problem which is addressed here is the design of integrated powerMOS transistors, which are used more and more widely in mobile applications. Applications are for instance DC-DC converters in processors or generally speaking power management systems.
The powerMOS transistors are typically designed in large arrays of elementary lateral MOS transistors, which are interconnected with meshes of metal on different layers. Viso allows to determine the global parameters and to investigate and improve the local contribution of the interconnect mesh.
The designer of powerMOS transistors needs to determine in a fast way several key characteristics of the powerMOS array he is designing. Among the most important ones are the on-resistance RDS,on and the input- and output – capacitances Ciss and Coss.
Integrated into standard design flows, Viso relies on the existing layout extraction tools of the major EDA software vendors. It concentrates on the key parameters of the powerMOS array with an extremely fast turnaround time. A typical analysis of an array of 6000 elementary transistors can be finished in less than 15 minutes. An additional analysis allows verifying design rules for electro-migration (EM) reliability.
A whitepaper on the design of PowerMOS arrays using Viso can be downloaded on the company’s webpage.
Founded in 2004, EdXact SA focuses on electronic design tools aimed at physical verification tasks. EdXact’s innovative model order reduction technology helps to accelerate extensive backend verifications in complex IC design cycles. EdXact is headquartered in Grenoble area, France with sales offices in California, Japan, Korea and Taiwan.
For additional information: http://www.edxact.com
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