Tanner EDA Announces All-New Digital Place and Route Tool in Release v16.1 of HiPer Silicon Design Suite

MONROVIA, California – April 16, 2014 – Tanner EDA, the catalyst for innovation and leader for design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and (ASICs), has released version 16.1 of the company’s HiPer Silicon™ design suite, including an all-new digital place and route tool, HiPer P&R™. HiPer P&R is optimized for the needs of big-Analog/little-Digital mixed signal designs on typical analog process nodes. The new addition HiPer P&R completes Tanner EDA’s end-to-end flow for analog/mixed signal designs.

HiPer P&R features:

  • Cost-effective, integrated digital place and route tool for mixed-signal designs
  • Clock tree synthesis
  • SDF timing extraction.
  • Support for standard digital formats, including LEF/DEF, Liberty, Verilog, and SDF

 “Tanner EDA users that are developing mixed-signal ICs, or doing large chip assembly projects, can now use HiPer P&R to cost-effectively implement their designs in-house. With no hard limits on gate count, design size or interconnect layers, HiPer P&R is integrated into the L-Edit SDL flow, providing tremendous flexibility and user control at every step of the process,” said Massimo Sivilotti,  Tanner EDA’s CTO and head of engineering. “By using industry standard input and output formats, HiPer P&R leverages foundry-provided PDKs, and can be easily integrated into existing toolflows.” 

Pricing and Availability

HiPer P&R v16.1 is available for the Windows® and Linux® operating systems. For additional information, visit the Tanner EDA website at www.tannereda.com, contact Tanner EDA Sales by phone (626-471-9701), or email Email Contact.

About Tanner EDA

Tanner EDA provides a complete line of EDA software solutions that drive innovation for the design, layout and verification of analog and mixed-signal (A/MS) integrated circuits (ICs) and MEMS. Customers are creating breakthrough applications in areas such as power management, displays and imaging, automotive, consumer electronics, life sciences, and RF devices. A low learning curve, high interoperability, and a powerful user interface improve design team productivity. Tanner EDA is the price/performance leader and the industry alternative for a complete design flow, improving total cost of ownership (TCO) and reducing EDA tool expense for its global customers. Capability and performance are matched by unparalleled customer support as well as an ecosystem of partners that bring advanced capabilities to A/MS designs.

Founded in 1988, Tanner EDA solutions deliver just the right mixture of features, functionality and usability. The company has shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries.

HiPer P&R, HiPer Verify, HiPer Silicon, Tanner Tools, L-Edit, S-Edit and W-Edit are trademarks of Tanner Research, Inc. Any other trademarks or trade names mentioned are the property of their respective owners.

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Media Contact :

Linda Marchant, Cayenne Communication LLC -- 919-451-0776 Email Contact


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