News by Design: Speed PCB Design, New OrCAD Look, DAC Approaches, May 2014

Packaging and PCB Design Tools and More at DAC

As complexity increases, we pick up the pace of innovation in packaging and board design products. Cadence’s Kevin Rinebold offered some insights in a Q&A we did recently. This edition of our newsletter offers a number of ways to speed your board design to combat complexity and stay on schedule. And for longtime OrCAD® fans, get ready for our new-look website! We think you’ll find it more useful and informative than ever. Lastly, DAC is just around the corner. Cadence will be out in force at San Francisco’s Moscone Convention Center the week of June 2. We hope to see you there!

Brian Fuller

   PCB Design, SI/PI Analysis, and Co-Design

New Website: Your Destination for All Things OrCAD

Cadence is excited to launch the new OrCAD website, delivering up-to-date datasheets, videos, and other useful information, as well as channel partner connections.

New Offering: Integrated Solution for Rapid Die-Package Interconnect Planning in OrbitIO Technology

Learn about a new solution built on Cadence® OrbitIO™ technology that significantly shortens die-package interconnect planning time by reducing iterations between silicon and package design teams.

Blog Post: Adding a View of Package Substrate in Your IC Layout Tool

Blogger Jeffrey Gallagher outlines how you can export a view of the package substrate and overlay it on your IC design canvas in Cadence’s digital design tools.

Blog Post: OrbitIO/SiP Digital Layout XL Co-Design Flow

Team Allegro presents highlights from a CDNLive Silicon Valley session on co-design. Two papers on OrbitIO system planner were presented, one from Faraday Technology and the other from Altera.

Exclusive Article: Accelerating PCB Design Authoring with Interface-Aware Design

Are your design authoring tools delivering the speed and ease of use you need to keep pace with your design cycle demands? What if you could apply a hierarchical interface-aware approach to accelerate your PCB design authoring and implementation process? Read this article to learn more.

Article: Three Ways that Allegro TimingVision Environment Speeds Up Timing Closure of High-Speed PCB Interfaces

Timing closure of advanced high-speed interfaces can be a time-consuming and frustrating iterative process. Learn how Cadence Allegro® TimingVision™ Environment can speed up the process.

White Paper: Team-Based Approach to PCB Power Integrity Analysis

Learn how a collaborative, team-based approach to PCB power integrity analysis is more efficient and delivers more impact at critical points in the design process.

Archived Webinar: Accelerate PCB Routing by Optimizing FPGA Pin Assignments

Learn ways to accelerate routing and reduce PCB layer counts by optimizing FPGA pin assignments during place-and-route planning in this hour-long session.

   Training Classes

Allegro PCB Editor Basic Techniques

Learn steps for designing a PCB, from loading logic and netlist data through producing manufacturing/NC output.


Allegro PCB Editor Intermediate Techniques

Gain a deeper understanding of the software, including features and tips, by using the constraint manager, auto-routing high-speed designs, and working with differential pairs.


Allegro Design Entry Using OrCAD Capture

In this class, you’ll start with some basic schematic library development and create and process a simple design. Then, you’ll progress into multi-sheet and hierarchical designs. 


   Cadence on the Road

Design Automation Conference – June 1-5; San Francisco, CA

See product demos and learn design tips and best practices at paper presentations, panels, and technology sessions. Also, don’t miss the popular Denali Party!  



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