San Francisco, CA — Design Automation Conference — June 2, 2014 — Semiconductor intellectual property provider CAST, Inc. is demonstrating here at DAC a new, high-performance, low-power, full-hardware H.265 video decoder core that handles next-generation video steams in real time without need for software computations running on a central processing unit (CPU). The new H.265-MPI-D Main Profile Intra HEVC Decoder Core is the first in a series of H.265 High Efficiency Video Coding cores CAST will offer, and will be available in the third quarter of this year.
The H.265-MPI-D is sourced from the Fraunhofer Heinrich Hertz Institute (HHI). Fraunhofer engineers participated in the standards effort leading to H.265 HEVC, and the core fully conforms to the resulting ISO/IEC 23008-2 HEVC and ITU-T H/265 industry standards. Fraunhofer HHI is also one of the few—and among the most highly-respected—sources for the complete H.265 compliance test streams used throughout the industry, and the core has been rigorously verified using them.
The decoder design is distinguished by clever use of internal and external memory. Its application-specific internal memory architecture enables reuse of already fetched data, which keeps more memory transfers within the chip to yield lower external memory bandwidth and power consumption. It also has a high tolerance to memory latency (delay), which is critical when expensive external memory is shared with other blocks such as a CPU. These benefits—coupled with the decoder’s full-hardware, CPU-less decoding ability—make the core a great match for any applications requiring real-time H.265 performance but having power, packaging, or budgetary constraints.
The H265-MPI-D HEVC Video Decoder Core joins CAST’s line of MCUs and MPUs, image and video compression codecs, GPUs and graphics accelerators, and other IP cores and subsystems for building competitive FPGA and ASIC systems.